tree bdabfcaac67ee4ab224aa5993010ddefbf8ba4db
parent 80baf649c2778bb8900cb9011bc712b89faddbdb
author Jason Gunthorpe <jgunthorpe@obsidianresearch.com> 1479767205 +0000
committer Alan Tull <atull@opensource.altera.com> 1480456308 -0600

fpga zynq: Fix incorrect ISR state on bootup

It is best practice to clear and mask all interrupts before
associating the IRQ, and this should be done after the clock
is enabled.

This corrects a bad result from zynq_fpga_ops_state on bootup
where left over latched values in INT_STS_OFFSET caused it to
report an unconfigured FPGA as configured.

After this change the boot up operating state for an unconfigured
FPGA reports 'unknown'.

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: Alan Tull <atull@opensource.altera.com>
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>