| commit | 34ac2c278b306cc3006dd5cbfaff4ec52065bf6f | [log] [tgz] |
|---|---|---|
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | Thu Feb 23 12:44:39 2017 +0200 |
| committer | Thierry Reding <treding@nvidia.com> | Mon Mar 20 14:04:45 2017 +0100 |
| tree | 1cac5e108c4f0c050fa796ed682777126beab16c | |
| parent | 9326947f2215e1816a9133b0b47e4c9200552777 [diff] |
clk: tegra: Fix ISP clock modelling The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model this as 1 mux/divider clock and child gate clocks. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>