Merge tag 'sh-pfc-for-v4.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.12
- Fixes and cleanups.
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 2fd688c..b532244 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -23,7 +23,8 @@
"allwinner,sun8i-h3-pinctrl"
"allwinner,sun8i-h3-r-pinctrl"
"allwinner,sun50i-a64-pinctrl"
- "allwinner,sun50i-h5-r-pinctrl"
+ "allwinner,sun50i-a64-r-pinctrl"
+ "allwinner,sun50i-h5-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 4722bc6..ee01ab5 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -19,11 +19,18 @@
defined as gpio sub-nodes of the pinmux controller.
Required properties for iomux controller:
- - compatible: one of "rockchip,rk1108-pinctrl", "rockchip,rk2928-pinctrl"
- "rockchip,rk3066a-pinctrl", "rockchip,rk3066b-pinctrl"
- "rockchip,rk3188-pinctrl", "rockchip,rk3228-pinctrl"
- "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
- "rockchip,rk3399-pinctrl"
+ - compatible: should be
+ "rockchip,rv1108-pinctrl": for Rockchip RV1108
+ "rockchip,rk2928-pinctrl": for Rockchip RK2928
+ "rockchip,rk3066a-pinctrl": for Rockchip RK3066a
+ "rockchip,rk3066b-pinctrl": for Rockchip RK3066b
+ "rockchip,rk3188-pinctrl": for Rockchip RK3188
+ "rockchip,rk3228-pinctrl": for Rockchip RK3228
+ "rockchip,rk3288-pinctrl": for Rockchip RK3288
+ "rockchip,rk3328-pinctrl": for Rockchip RK3328
+ "rockchip,rk3368-pinctrl": for Rockchip RK3368
+ "rockchip,rk3399-pinctrl": for Rockchip RK3399
+
- rockchip,grf: phandle referencing a syscon providing the
"general register files"
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
index d6194bf..6c8fc19 100644
--- a/arch/arm/boot/dts/rk1108.dtsi
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -222,7 +222,7 @@
};
pinctrl: pinctrl {
- compatible = "rockchip,rk1108-pinctrl";
+ compatible = "rockchip,rv1108-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmugrf>;
#address-cells = <1>;
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
index 76f62bd..5b49952 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
@@ -198,9 +198,19 @@ static int aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
* them. This may mean that certain functions cannot be
* deconfigured and is the reason we re-evaluate after writing
* all descriptor bits.
+ *
+ * Port D and port E GPIO loopback modes are the only exception
+ * as those are commonly used with front-panel buttons to allow
+ * normal operation of the host when the BMC is powered off or
+ * fails to boot. Once the BMC has booted, the loopback mode
+ * must be disabled for the BMC to control host power-on and
+ * reset.
*/
- if ((desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2) &&
- desc->ip == ASPEED_IP_SCU)
+ if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
+ !(desc->mask & (BIT(21) | BIT(22))))
+ continue;
+
+ if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
continue;
ret = regmap_update_bits(maps[desc->ip], desc->reg,
diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
index 3ca925d..af5e904 100644
--- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
+++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
@@ -99,7 +99,7 @@ struct iproc_gpio {
void __iomem *base;
void __iomem *io_ctrl;
- spinlock_t lock;
+ raw_spinlock_t lock;
struct gpio_chip gc;
unsigned num_banks;
@@ -221,9 +221,9 @@ static void iproc_gpio_irq_mask(struct irq_data *d)
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
iproc_gpio_irq_set_mask(d, false);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
}
static void iproc_gpio_irq_unmask(struct irq_data *d)
@@ -232,9 +232,9 @@ static void iproc_gpio_irq_unmask(struct irq_data *d)
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
iproc_gpio_irq_set_mask(d, true);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
}
static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
@@ -274,13 +274,13 @@ static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
return -EINVAL;
}
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
level_triggered);
iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
rising_or_high);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev,
"gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
@@ -328,9 +328,9 @@ static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
@@ -343,10 +343,10 @@ static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
@@ -358,9 +358,9 @@ static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
}
@@ -461,7 +461,7 @@ static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
{
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
if (disable) {
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false);
@@ -471,7 +471,7 @@ static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true);
}
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
@@ -483,10 +483,10 @@ static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
{
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
*disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
*pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
}
static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
@@ -515,7 +515,7 @@ static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
strength);
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
strength = (strength / 2) - 1;
for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
val = readl(base + offset);
@@ -524,7 +524,7 @@ static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
writel(val, base + offset);
offset += 4;
}
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
@@ -548,7 +548,7 @@ static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
shift = IPROC_GPIO_SHIFT(gpio);
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
*strength = 0;
for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
val = readl(base + offset) & BIT(shift);
@@ -559,7 +559,7 @@ static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
/* convert to mA */
*strength = (*strength + 1) * 2;
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
@@ -769,7 +769,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
return -ENODEV;
}
- spin_lock_init(&chip->lock);
+ raw_spin_lock_init(&chip->lock);
gc = &chip->gc;
gc->base = -1;
diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
index 91ea32d..2244243 100644
--- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
+++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
@@ -73,7 +73,7 @@ struct nsp_gpio {
struct pinctrl_dev *pctl;
struct pinctrl_desc pctldesc;
struct irq_domain *irq_domain;
- spinlock_t lock;
+ raw_spinlock_t lock;
};
enum base_type {
@@ -203,9 +203,9 @@ static void nsp_gpio_irq_mask(struct irq_data *d)
struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
nsp_gpio_irq_set_mask(d, false);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
}
static void nsp_gpio_irq_unmask(struct irq_data *d)
@@ -213,9 +213,9 @@ static void nsp_gpio_irq_unmask(struct irq_data *d)
struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
nsp_gpio_irq_set_mask(d, true);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
}
static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
@@ -226,7 +226,7 @@ static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
bool falling;
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
@@ -250,13 +250,13 @@ static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
default:
dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
type);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
return -EINVAL;
}
nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
level_low ? "true" : "false", falling ? "true" : "false");
@@ -295,9 +295,9 @@ static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
return 0;
@@ -309,10 +309,10 @@ static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
return 0;
@@ -323,9 +323,9 @@ static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
}
@@ -381,10 +381,10 @@ static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
{
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
gpio, pull_up, pull_down);
@@ -396,10 +396,10 @@ static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
{
unsigned long flags;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
*pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
*pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
}
static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
@@ -417,7 +417,7 @@ static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
offset = NSP_GPIO_DRV_CTRL;
dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
strength);
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
strength = (strength / 2) - 1;
for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
val = readl(chip->io_ctrl + offset);
@@ -426,7 +426,7 @@ static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
writel(val, chip->io_ctrl + offset);
offset += 4;
}
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
@@ -442,7 +442,7 @@ static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
offset = NSP_GPIO_DRV_CTRL;
shift = gpio;
- spin_lock_irqsave(&chip->lock, flags);
+ raw_spin_lock_irqsave(&chip->lock, flags);
*strength = 0;
for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
val = readl(chip->io_ctrl + offset) & BIT(shift);
@@ -453,7 +453,7 @@ static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
/* convert to mA */
*strength = (*strength + 1) * 2;
- spin_unlock_irqrestore(&chip->lock, flags);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
@@ -660,7 +660,7 @@ static int nsp_gpio_probe(struct platform_device *pdev)
return PTR_ERR(chip->io_ctrl);
}
- spin_lock_init(&chip->lock);
+ raw_spin_lock_init(&chip->lock);
gc = &chip->gc;
gc->base = -1;
gc->can_sleep = false;
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index d690465..37be238 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -525,7 +525,7 @@ pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin);
/**
- * pinctrl_remove_gpio_range() - remove a range of GPIOs fro a pin controller
+ * pinctrl_remove_gpio_range() - remove a range of GPIOs from a pin controller
* @pctldev: pin controller device to remove the range from
* @range: the GPIO range to remove
*/
@@ -1062,7 +1062,7 @@ static struct pinctrl *create_pinctrl(struct device *dev,
mutex_unlock(&pinctrl_maps_mutex);
if (ret < 0) {
- /* If some other error than deferral occured, return here */
+ /* If some other error than deferral occurred, return here */
pinctrl_free(p, false);
return ERR_PTR(ret);
}
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index f80134e..83640af 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -148,6 +148,7 @@ struct chv_community {
size_t ngpio_ranges;
size_t ngpios;
size_t nirqs;
+ acpi_adr_space_type acpi_space_id;
};
struct chv_pin_context {
@@ -404,6 +405,7 @@ static const struct chv_community southwest_community = {
* trigger GPEs.
*/
.nirqs = 8,
+ .acpi_space_id = 0x91,
};
static const struct pinctrl_pin_desc north_pins[] = {
@@ -493,6 +495,7 @@ static const struct chv_community north_community = {
* GPEs.
*/
.nirqs = 8,
+ .acpi_space_id = 0x92,
};
static const struct pinctrl_pin_desc east_pins[] = {
@@ -536,6 +539,7 @@ static const struct chv_community east_community = {
.ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
.ngpios = ARRAY_SIZE(east_pins),
.nirqs = 16,
+ .acpi_space_id = 0x93,
};
static const struct pinctrl_pin_desc southeast_pins[] = {
@@ -662,6 +666,7 @@ static const struct chv_community southeast_community = {
.ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
.ngpios = ARRAY_SIZE(southeast_pins),
.nirqs = 16,
+ .acpi_space_id = 0x94,
};
static const struct chv_community *chv_communities[] = {
@@ -1586,11 +1591,34 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
return 0;
}
+static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
+ acpi_physical_address address, u32 bits, u64 *value,
+ void *handler_context, void *region_context)
+{
+ struct chv_pinctrl *pctrl = region_context;
+ unsigned long flags;
+ acpi_status ret = AE_OK;
+
+ raw_spin_lock_irqsave(&chv_lock, flags);
+
+ if (function == ACPI_WRITE)
+ chv_writel((u32)(*value), pctrl->regs + (u32)address);
+ else if (function == ACPI_READ)
+ *value = readl(pctrl->regs + (u32)address);
+ else
+ ret = AE_BAD_PARAMETER;
+
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
+
+ return ret;
+}
+
static int chv_pinctrl_probe(struct platform_device *pdev)
{
struct chv_pinctrl *pctrl;
struct acpi_device *adev;
struct resource *res;
+ acpi_status status;
int ret, irq, i;
adev = ACPI_COMPANION(&pdev->dev);
@@ -1646,11 +1674,29 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
if (ret)
return ret;
+ status = acpi_install_address_space_handler(adev->handle,
+ pctrl->community->acpi_space_id,
+ chv_pinctrl_mmio_access_handler,
+ NULL, pctrl);
+ if (ACPI_FAILURE(status))
+ dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
+
platform_set_drvdata(pdev, pctrl);
return 0;
}
+static int chv_pinctrl_remove(struct platform_device *pdev)
+{
+ struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
+
+ acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
+ pctrl->community->acpi_space_id,
+ chv_pinctrl_mmio_access_handler);
+
+ return 0;
+}
+
#ifdef CONFIG_PM_SLEEP
static int chv_pinctrl_suspend_noirq(struct device *dev)
{
@@ -1758,6 +1804,7 @@ MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
static struct platform_driver chv_pinctrl_driver = {
.probe = chv_pinctrl_probe,
+ .remove = chv_pinctrl_remove,
.driver = {
.name = "cherryview-pinctrl",
.pm = &chv_pinctrl_pm_ops,
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index 4ab94a8..a0a7936 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -195,8 +195,19 @@ static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) };
static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) };
static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) };
+static const unsigned int pwm_a_pins[] = { PIN(GPIOX_6, EE_OFF) };
+
+static const unsigned int pwm_b_pins[] = { PIN(GPIODV_29, EE_OFF) };
+
+static const unsigned int pwm_c_pins[] = { PIN(GPIOZ_15, EE_OFF) };
+
+static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, EE_OFF) };
+
static const unsigned int pwm_e_pins[] = { PIN(GPIOX_16, EE_OFF) };
+static const unsigned int pwm_f_clk_pins[] = { PIN(GPIOCLK_1, EE_OFF) };
+static const unsigned int pwm_f_x_pins[] = { PIN(GPIOX_7, EE_OFF) };
+
static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, EE_OFF) };
static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, EE_OFF) };
static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, EE_OFF) };
@@ -225,6 +236,9 @@ static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) };
static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) };
+static const unsigned int pwm_ao_a_3_pins[] = { PIN(GPIOAO_3, 0) };
+static const unsigned int pwm_ao_a_8_pins[] = { PIN(GPIOAO_8, 0) };
+
static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_9, 0) };
static struct meson_pmx_group meson_gxl_periphs_groups[] = {
@@ -350,7 +364,9 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GROUP(uart_rts_a, 5, 16),
GROUP(uart_tx_c, 5, 13),
GROUP(uart_rx_c, 5, 12),
+ GROUP(pwm_a, 5, 25),
GROUP(pwm_e, 5, 15),
+ GROUP(pwm_f_x, 5, 14),
/* Bank Z */
GROUP(eth_mdio, 4, 22),
@@ -367,6 +383,7 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GROUP(eth_txd1, 4, 12),
GROUP(eth_txd2, 4, 11),
GROUP(eth_txd3, 4, 10),
+ GROUP(pwm_c, 3, 20),
/* Bank H */
GROUP(hdmi_hpd, 6, 31),
@@ -382,6 +399,8 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GROUP(i2c_sda_b, 1, 12),
GROUP(i2c_sck_c, 1, 11),
GROUP(i2c_sda_c, 1, 10),
+ GROUP(pwm_b, 2, 11),
+ GROUP(pwm_d, 2, 12),
/* Bank BOOT */
GROUP(emmc_nand_d07, 7, 31),
@@ -404,6 +423,9 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GROUP(sdcard_d2, 6, 0),
GROUP(sdcard_cmd, 6, 2),
GROUP(sdcard_clk, 6, 3),
+
+ /* Bank CLK */
+ GROUP(pwm_f_clk, 8, 30),
};
static struct meson_pmx_group meson_gxl_aobus_groups[] = {
@@ -428,6 +450,8 @@ static struct meson_pmx_group meson_gxl_aobus_groups[] = {
GROUP(uart_cts_ao_b, 0, 8),
GROUP(uart_rts_ao_b, 0, 7),
GROUP(remote_input_ao, 0, 0),
+ GROUP(pwm_ao_a_3, 0, 22),
+ GROUP(pwm_ao_a_8, 0, 17),
GROUP(pwm_ao_b, 0, 3),
};
@@ -513,10 +537,30 @@ static const char * const eth_groups[] = {
"eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3",
};
+static const char * const pwm_a_groups[] = {
+ "pwm_a",
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b",
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c",
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d",
+};
+
static const char * const pwm_e_groups[] = {
"pwm_e",
};
+static const char * const pwm_f_groups[] = {
+ "pwm_f_clk", "pwm_f_x",
+};
+
static const char * const hdmi_hpd_groups[] = {
"hdmi_hpd",
};
@@ -542,6 +586,10 @@ static const char * const remote_input_ao_groups[] = {
"remote_input_ao",
};
+static const char * const pwm_ao_a_groups[] = {
+ "pwm_ao_a_3", "pwm_ao_a_8",
+};
+
static const char * const pwm_ao_b_groups[] = {
"pwm_ao_b",
};
@@ -559,7 +607,12 @@ static struct meson_pmx_func meson_gxl_periphs_functions[] = {
FUNCTION(i2c_b),
FUNCTION(i2c_c),
FUNCTION(eth),
+ FUNCTION(pwm_a),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
FUNCTION(pwm_e),
+ FUNCTION(pwm_f),
FUNCTION(hdmi_hpd),
FUNCTION(hdmi_i2c),
};
@@ -569,6 +622,7 @@ static struct meson_pmx_func meson_gxl_aobus_functions[] = {
FUNCTION(uart_ao),
FUNCTION(uart_ao_b),
FUNCTION(remote_input_ao),
+ FUNCTION(pwm_ao_a),
FUNCTION(pwm_ao_b),
};
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index ce3335a..720a19f 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -187,7 +187,7 @@ static const struct pinconf_generic_params dt_params[] = {
* @ncfg: Number of entries in @cfg
*
* Parse the config options described in @params from @np and puts the result
- * in @cfg. @cfg does not need to be empty, entries are added beggining at
+ * in @cfg. @cfg does not need to be empty, entries are added beginning at
* @ncfg. @ncfg is updated to reflect the number of entries after parsing. @cfg
* needs to have enough memory allocated to hold all possible entries.
*/
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index c1c1ccc..a02dba3 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -284,7 +284,7 @@ void pinconf_show_setting(struct seq_file *s,
}
/*
- * FIXME: We should really get the pin controler to dump the config
+ * FIXME: We should really get the pin controller to dump the config
* values, so they can be decoded to something meaningful.
*/
pinconf_show_config(s, pctldev, setting->data.configs.configs,
@@ -473,7 +473,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
* "config_pin" or "config_group", alternatives like config_mux are not
* supported yet.
* <devicename> <state> <name> are values that should match the pinctrl-maps
- * <newvalue> reflects the new config and is driver dependant
+ * <newvalue> reflects the new config and is driver dependent
*/
static ssize_t pinconf_dbg_config_write(struct file *file,
const char __user *user_buf, size_t count, loff_t *ppos)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index d69e357..043ac9b 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -41,11 +41,11 @@ static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
u32 pin_reg;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
writel(pin_reg, gpio_dev->base + offset * 4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return 0;
}
@@ -57,7 +57,7 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
unsigned long flags;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg |= BIT(OUTPUT_ENABLE_OFF);
if (value)
@@ -65,7 +65,7 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
else
pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
writel(pin_reg, gpio_dev->base + offset * 4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return 0;
}
@@ -76,9 +76,9 @@ static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
unsigned long flags;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return !!(pin_reg & BIT(PIN_STS_OFF));
}
@@ -89,14 +89,14 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
unsigned long flags;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
if (value)
pin_reg |= BIT(OUTPUT_VALUE_OFF);
else
pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
writel(pin_reg, gpio_dev->base + offset * 4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
@@ -108,7 +108,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
unsigned long flags;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
if (debounce) {
@@ -159,7 +159,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
pin_reg &= ~DB_CNTRl_MASK;
}
writel(pin_reg, gpio_dev->base + offset * 4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret;
}
@@ -224,9 +224,9 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
}
for (; i < pin_num; i++) {
seq_printf(s, "pin%d\t", i);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + i * 4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
interrupt_enable = "interrupt is enabled|";
@@ -331,12 +331,12 @@ static void amd_gpio_irq_enable(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
pin_reg |= BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static void amd_gpio_irq_disable(struct irq_data *d)
@@ -346,12 +346,12 @@ static void amd_gpio_irq_disable(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static void amd_gpio_irq_mask(struct irq_data *d)
@@ -361,11 +361,11 @@ static void amd_gpio_irq_mask(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static void amd_gpio_irq_unmask(struct irq_data *d)
@@ -375,11 +375,11 @@ static void amd_gpio_irq_unmask(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg |= BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static void amd_gpio_irq_eoi(struct irq_data *d)
@@ -389,11 +389,11 @@ static void amd_gpio_irq_eoi(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
reg |= EOI_MASK;
writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
@@ -404,7 +404,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
/* Ignore the settings coming from the client and
@@ -469,7 +469,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret;
}
@@ -511,14 +511,14 @@ static void amd_gpio_irq_handler(struct irq_desc *desc)
chained_irq_enter(chip, desc);
/*enable GPIO interrupt again*/
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
reg64 = reg;
reg64 = reg64 << 32;
reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
reg64 |= reg;
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
/*
* first 46 bits indicates interrupt status.
@@ -546,11 +546,11 @@ static void amd_gpio_irq_handler(struct irq_desc *desc)
if (handled == 0)
handle_bad_irq(desc);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
reg |= EOI_MASK;
writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
chained_irq_exit(chip, desc);
}
@@ -602,9 +602,9 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev,
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + pin*4);
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
arg = pin_reg & DB_TMR_OUT_MASK;
@@ -644,7 +644,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
enum pin_config_param param;
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
- spin_lock_irqsave(&gpio_dev->lock, flags);
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
@@ -683,7 +683,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
writel(pin_reg, gpio_dev->base + pin*4);
}
- spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret;
}
@@ -751,7 +751,7 @@ static int amd_gpio_probe(struct platform_device *pdev)
if (!gpio_dev)
return -ENOMEM;
- spin_lock_init(&gpio_dev->lock);
+ raw_spin_lock_init(&gpio_dev->lock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h
index c03f778..5b1cb96 100644
--- a/drivers/pinctrl/pinctrl-amd.h
+++ b/drivers/pinctrl/pinctrl-amd.h
@@ -87,7 +87,7 @@ struct amd_function {
};
struct amd_gpio {
- spinlock_t lock;
+ raw_spinlock_t lock;
void __iomem *base;
const struct amd_pingroup *groups;
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 7813599..bd4b63f 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -59,7 +59,7 @@
#define GPIO_LS_SYNC 0x60
enum rockchip_pinctrl_type {
- RK1108,
+ RV1108,
RK2928,
RK3066B,
RK3188,
@@ -75,6 +75,8 @@ enum rockchip_pinctrl_type {
#define IOMUX_WIDTH_4BIT BIT(1)
#define IOMUX_SOURCE_PMU BIT(2)
#define IOMUX_UNROUTED BIT(3)
+#define IOMUX_WIDTH_3BIT BIT(4)
+#define IOMUX_RECALCED BIT(5)
/**
* @type: iomux variant using IOMUX_* constants
@@ -304,6 +306,11 @@ struct rockchip_pin_ctrl {
void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
+ void (*iomux_recalc)(u8 bank_num, int pin, int *reg,
+ u8 *bit, int *mask);
+ int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit);
};
struct rockchip_pin_config {
@@ -355,6 +362,22 @@ struct rockchip_pinctrl {
unsigned int nfunctions;
};
+/**
+ * struct rockchip_mux_recalced_data: represent a pin iomux data.
+ * @num: bank number.
+ * @pin: pin number.
+ * @bit: index at register.
+ * @reg: register offset.
+ * @mask: mask bit
+ */
+struct rockchip_mux_recalced_data {
+ u8 num;
+ u8 pin;
+ u8 reg;
+ u8 bit;
+ u8 mask;
+};
+
static struct regmap_config rockchip_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@@ -514,13 +537,57 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
* Hardware access
*/
+static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
+ {
+ .num = 2,
+ .pin = 12,
+ .reg = 0x24,
+ .bit = 8,
+ .mask = 0x3
+ }, {
+ .num = 2,
+ .pin = 15,
+ .reg = 0x28,
+ .bit = 0,
+ .mask = 0x7
+ }, {
+ .num = 2,
+ .pin = 23,
+ .reg = 0x30,
+ .bit = 14,
+ .mask = 0x3
+ },
+};
+
+static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg,
+ u8 *bit, int *mask)
+{
+ const struct rockchip_mux_recalced_data *data = NULL;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++)
+ if (rk3328_mux_recalced_data[i].num == bank_num &&
+ rk3328_mux_recalced_data[i].pin == pin) {
+ data = &rk3328_mux_recalced_data[i];
+ break;
+ }
+
+ if (!data)
+ return;
+
+ *reg = data->reg;
+ *mask = data->mask;
+ *bit = data->bit;
+}
+
static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
{
struct rockchip_pinctrl *info = bank->drvdata;
+ struct rockchip_pin_ctrl *ctrl = info->ctrl;
int iomux_num = (pin / 8);
struct regmap *regmap;
unsigned int val;
- int reg, ret, mask;
+ int reg, ret, mask, mux_type;
u8 bit;
if (iomux_num > 3)
@@ -538,16 +605,26 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
? info->regmap_pmu : info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
- mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
+ mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
- if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
+ if (mux_type & IOMUX_WIDTH_4BIT) {
if ((pin % 8) >= 4)
reg += 0x4;
bit = (pin % 4) * 4;
+ mask = 0xf;
+ } else if (mux_type & IOMUX_WIDTH_3BIT) {
+ if ((pin % 8) >= 5)
+ reg += 0x4;
+ bit = (pin % 8 % 5) * 3;
+ mask = 0x7;
} else {
bit = (pin % 8) * 2;
+ mask = 0x3;
}
+ if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
+ ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask);
+
ret = regmap_read(regmap, reg, &val);
if (ret)
return ret;
@@ -571,9 +648,10 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl *info = bank->drvdata;
+ struct rockchip_pin_ctrl *ctrl = info->ctrl;
int iomux_num = (pin / 8);
struct regmap *regmap;
- int reg, ret, mask;
+ int reg, ret, mask, mux_type;
unsigned long flags;
u8 bit;
u32 data, rmask;
@@ -603,16 +681,26 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
? info->regmap_pmu : info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
- mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
+ mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
- if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
+ if (mux_type & IOMUX_WIDTH_4BIT) {
if ((pin % 8) >= 4)
reg += 0x4;
bit = (pin % 4) * 4;
+ mask = 0xf;
+ } else if (mux_type & IOMUX_WIDTH_3BIT) {
+ if ((pin % 8) >= 5)
+ reg += 0x4;
+ bit = (pin % 8 % 5) * 3;
+ mask = 0x7;
} else {
bit = (pin % 8) * 2;
+ mask = 0x3;
}
+ if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
+ ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask);
+
spin_lock_irqsave(&bank->slock, flags);
data = (mask << (bit + 16));
@@ -625,13 +713,13 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
return ret;
}
-#define RK1108_PULL_PMU_OFFSET 0x10
-#define RK1108_PULL_OFFSET 0x110
-#define RK1108_PULL_PINS_PER_REG 8
-#define RK1108_PULL_BITS_PER_PIN 2
-#define RK1108_PULL_BANK_STRIDE 16
+#define RV1108_PULL_PMU_OFFSET 0x10
+#define RV1108_PULL_OFFSET 0x110
+#define RV1108_PULL_PINS_PER_REG 8
+#define RV1108_PULL_BITS_PER_PIN 2
+#define RV1108_PULL_BANK_STRIDE 16
-static void rk1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
@@ -640,27 +728,27 @@ static void rk1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
- *reg = RK1108_PULL_PMU_OFFSET;
+ *reg = RV1108_PULL_PMU_OFFSET;
} else {
- *reg = RK1108_PULL_OFFSET;
+ *reg = RV1108_PULL_OFFSET;
*regmap = info->regmap_base;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
- *reg += bank->bank_num * RK1108_PULL_BANK_STRIDE;
+ *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
}
- *reg += ((pin_num / RK1108_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK1108_PULL_PINS_PER_REG);
- *bit *= RK1108_PULL_BITS_PER_PIN;
+ *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
+ *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
+ *bit *= RV1108_PULL_BITS_PER_PIN;
}
-#define RK1108_DRV_PMU_OFFSET 0x20
-#define RK1108_DRV_GRF_OFFSET 0x210
-#define RK1108_DRV_BITS_PER_PIN 2
-#define RK1108_DRV_PINS_PER_REG 8
-#define RK1108_DRV_BANK_STRIDE 16
+#define RV1108_DRV_PMU_OFFSET 0x20
+#define RV1108_DRV_GRF_OFFSET 0x210
+#define RV1108_DRV_BITS_PER_PIN 2
+#define RV1108_DRV_PINS_PER_REG 8
+#define RV1108_DRV_BANK_STRIDE 16
-static void rk1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
@@ -669,19 +757,19 @@ static void rk1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
- *reg = RK1108_DRV_PMU_OFFSET;
+ *reg = RV1108_DRV_PMU_OFFSET;
} else {
*regmap = info->regmap_base;
- *reg = RK1108_DRV_GRF_OFFSET;
+ *reg = RV1108_DRV_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
- *reg += bank->bank_num * RK1108_DRV_BANK_STRIDE;
+ *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
}
- *reg += ((pin_num / RK1108_DRV_PINS_PER_REG) * 4);
- *bit = pin_num % RK1108_DRV_PINS_PER_REG;
- *bit *= RK1108_DRV_BITS_PER_PIN;
+ *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RV1108_DRV_PINS_PER_REG;
+ *bit *= RV1108_DRV_BITS_PER_PIN;
}
#define RK2928_PULL_OFFSET 0x118
@@ -1183,7 +1271,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
return !(data & BIT(bit))
? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
: PIN_CONFIG_BIAS_DISABLE;
- case RK1108:
+ case RV1108:
case RK3188:
case RK3288:
case RK3368:
@@ -1230,7 +1318,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
spin_unlock_irqrestore(&bank->slock, flags);
break;
- case RK1108:
+ case RV1108:
case RK3188:
case RK3288:
case RK3368:
@@ -1270,6 +1358,79 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
return ret;
}
+#define RK3328_SCHMITT_BITS_PER_PIN 1
+#define RK3328_SCHMITT_PINS_PER_REG 16
+#define RK3328_SCHMITT_BANK_STRIDE 8
+#define RK3328_SCHMITT_GRF_OFFSET 0x380
+
+static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+ *reg = RK3328_SCHMITT_GRF_OFFSET;
+
+ *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
+ *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
+
+ return 0;
+}
+
+static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+ struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit;
+ u32 data;
+
+ ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(regmap, reg, &data);
+ if (ret)
+ return ret;
+
+ data >>= bit;
+ return data & 0x1;
+}
+
+static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+ struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ struct regmap *regmap;
+ int reg, ret;
+ unsigned long flags;
+ u8 bit;
+ u32 data, rmask;
+
+ dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
+ bank->bank_num, pin_num, enable);
+
+ ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
+ if (ret)
+ return ret;
+
+ spin_lock_irqsave(&bank->slock, flags);
+
+ /* enable the write to the equivalent lower bits */
+ data = BIT(bit + 16) | (enable << bit);
+ rmask = BIT(bit + 16) | BIT(bit);
+
+ ret = regmap_update_bits(regmap, reg, rmask, data);
+ spin_unlock_irqrestore(&bank->slock, flags);
+
+ return ret;
+}
+
/*
* Pinmux_ops handling
*/
@@ -1420,7 +1581,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
pull == PIN_CONFIG_BIAS_DISABLE);
case RK3066B:
return pull ? false : true;
- case RK1108:
+ case RV1108:
case RK3188:
case RK3288:
case RK3368:
@@ -1489,6 +1650,15 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
if (rc < 0)
return rc;
break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (!info->ctrl->schmitt_calc_reg)
+ return -ENOTSUPP;
+
+ rc = rockchip_set_schmitt(bank,
+ pin - bank->pin_base, arg);
+ if (rc < 0)
+ return rc;
+ break;
default:
return -ENOTSUPP;
break;
@@ -1549,6 +1719,16 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
arg = rc;
break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (!info->ctrl->schmitt_calc_reg)
+ return -ENOTSUPP;
+
+ rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
+ if (rc < 0)
+ return rc;
+
+ arg = rc;
+ break;
default:
return -ENOTSUPP;
break;
@@ -2061,7 +2241,7 @@ static void rockchip_irq_resume(struct irq_data *d)
clk_disable(bank->clk);
}
-static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
+static void rockchip_irq_enable(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
@@ -2070,7 +2250,7 @@ static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
irq_gc_mask_clr_bit(d);
}
-static void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
+static void rockchip_irq_disable(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
@@ -2137,9 +2317,10 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
gc->chip_types[0].regs.mask = GPIO_INTMASK;
gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
- gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
- gc->chip_types[0].chip.irq_unmask =
- rockchip_irq_gc_mask_clr_bit;
+ gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
+ gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
+ gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
+ gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
@@ -2359,7 +2540,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
* Increase offset according to iomux width.
* 4bit iomux'es are spread over two registers.
*/
- inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
+ inc = (iom->type & (IOMUX_WIDTH_4BIT |
+ IOMUX_WIDTH_3BIT)) ? 8 : 4;
if (iom->type & IOMUX_SOURCE_PMU)
pmu_offs += inc;
else
@@ -2518,7 +2700,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
return 0;
}
-static struct rockchip_pin_bank rk1108_pin_banks[] = {
+static struct rockchip_pin_bank rv1108_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
@@ -2528,15 +2710,15 @@ static struct rockchip_pin_bank rk1108_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
};
-static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
- .pin_banks = rk1108_pin_banks,
- .nr_banks = ARRAY_SIZE(rk1108_pin_banks),
- .label = "RK1108-GPIO",
- .type = RK1108,
+static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
+ .pin_banks = rv1108_pin_banks,
+ .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
+ .label = "RV1108-GPIO",
+ .type = RV1108,
.grf_mux_offset = 0x10,
.pmu_mux_offset = 0x0,
- .pull_calc_reg = rk1108_calc_pull_reg_and_bit,
- .drv_calc_reg = rk1108_calc_drv_reg_and_bit,
+ .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
+ .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
};
static struct rockchip_pin_bank rk2928_pin_banks[] = {
@@ -2679,6 +2861,32 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
.drv_calc_reg = rk3288_calc_drv_reg_and_bit,
};
+static struct rockchip_pin_bank rk3328_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
+ IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
+ IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
+ 0),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
+ IOMUX_WIDTH_3BIT,
+ IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
+ 0,
+ 0),
+};
+
+static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
+ .pin_banks = rk3328_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
+ .label = "RK3328-GPIO",
+ .type = RK3288,
+ .grf_mux_offset = 0x0,
+ .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
+ .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
+ .iomux_recalc = rk3328_recalc_mux,
+ .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
+};
+
static struct rockchip_pin_bank rk3368_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
@@ -2768,8 +2976,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
};
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
- { .compatible = "rockchip,rk1108-pinctrl",
- .data = (void *)&rk1108_pin_ctrl },
+ { .compatible = "rockchip,rv1108-pinctrl",
+ .data = (void *)&rv1108_pin_ctrl },
{ .compatible = "rockchip,rk2928-pinctrl",
.data = (void *)&rk2928_pin_ctrl },
{ .compatible = "rockchip,rk3036-pinctrl",
@@ -2784,6 +2992,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = (void *)&rk3228_pin_ctrl },
{ .compatible = "rockchip,rk3288-pinctrl",
.data = (void *)&rk3288_pin_ctrl },
+ { .compatible = "rockchip,rk3328-pinctrl",
+ .data = (void *)&rk3328_pin_ctrl },
{ .compatible = "rockchip,rk3368-pinctrl",
.data = (void *)&rk3368_pin_ctrl },
{ .compatible = "rockchip,rk3399-pinctrl",
diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index f448534..bb3ce5c 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -35,10 +35,14 @@ static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
/* A reasonable limit to the number of GPIOS */
#define MAX_GPIOS 256
+/* maximum size of each gpio name (enough room for "gpioXXX" + null) */
+#define NAME_SIZE 8
+
static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
{
struct pinctrl_pin_desc *pins;
struct msm_pingroup *groups;
+ char (*names)[NAME_SIZE];
unsigned int i;
u32 num_gpios;
int ret;
@@ -59,15 +63,21 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
groups = devm_kcalloc(&pdev->dev, num_gpios,
sizeof(struct msm_pingroup), GFP_KERNEL);
+ names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
- if (!pins || !groups)
+ if (!pins || !groups || !names)
return -ENOMEM;
for (i = 0; i < num_gpios; i++) {
- pins[i].number = i;
+ snprintf(names[i], NAME_SIZE, "gpio%u", i);
- groups[i].npins = 1,
+ pins[i].number = i;
+ pins[i].name = names[i];
+
+ groups[i].npins = 1;
+ groups[i].name = names[i];
groups[i].pins = &pins[i].number;
+
groups[i].ctl_reg = 0x10000 * i;
groups[i].io_reg = 0x04 + 0x10000 * i;
groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index f9ddba7..0d2989d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -566,13 +566,11 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
{
const struct samsung_pin_bank_type *type;
struct samsung_pin_bank *bank;
- struct samsung_pinctrl_drv_data *drvdata;
void __iomem *reg;
u32 data, mask, shift;
bank = gpiochip_get_data(gc);
type = bank->type;
- drvdata = bank->drvdata;
reg = bank->pctl_base + bank->pctl_offset
+ type->reg_offset[PINCFG_TYPE_FUNC];
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c
index 600d642..1efa315 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c
@@ -352,7 +352,7 @@ struct atlas7_gpio_chip {
void __iomem *reg;
struct clk *clk;
int nbank;
- spinlock_t lock;
+ raw_spinlock_t lock;
struct gpio_chip chip;
struct atlas7_gpio_bank banks[0];
};
@@ -5650,13 +5650,13 @@ static void atlas7_gpio_irq_ack(struct irq_data *d)
pin_in_bank = d->hwirq - bank->gpio_offset;
ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
val = readl(ctrl_reg);
/* clear interrupt status */
writel(val, ctrl_reg);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
}
static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
@@ -5681,11 +5681,11 @@ static void atlas7_gpio_irq_mask(struct irq_data *d)
struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
unsigned long flags;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
__atlas7_gpio_irq_mask(a7gc, d->hwirq);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
}
static void atlas7_gpio_irq_unmask(struct irq_data *d)
@@ -5701,14 +5701,14 @@ static void atlas7_gpio_irq_unmask(struct irq_data *d)
pin_in_bank = d->hwirq - bank->gpio_offset;
ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
val = readl(ctrl_reg);
val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
writel(val, ctrl_reg);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
}
static int atlas7_gpio_irq_type(struct irq_data *d,
@@ -5725,7 +5725,7 @@ static int atlas7_gpio_irq_type(struct irq_data *d,
pin_in_bank = d->hwirq - bank->gpio_offset;
ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
val = readl(ctrl_reg);
val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
@@ -5768,7 +5768,7 @@ static int atlas7_gpio_irq_type(struct irq_data *d,
writel(val, ctrl_reg);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
return 0;
}
@@ -5863,7 +5863,7 @@ static int atlas7_gpio_request(struct gpio_chip *chip,
if (pinctrl_request_gpio(chip->base + gpio))
return -ENODEV;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
/*
* default status:
@@ -5872,7 +5872,7 @@ static int atlas7_gpio_request(struct gpio_chip *chip,
__atlas7_gpio_set_input(a7gc, gpio);
__atlas7_gpio_irq_mask(a7gc, gpio);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
return 0;
}
@@ -5883,12 +5883,12 @@ static void atlas7_gpio_free(struct gpio_chip *chip,
struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
unsigned long flags;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
__atlas7_gpio_irq_mask(a7gc, gpio);
__atlas7_gpio_set_input(a7gc, gpio);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
pinctrl_free_gpio(chip->base + gpio);
}
@@ -5899,11 +5899,11 @@ static int atlas7_gpio_direction_input(struct gpio_chip *chip,
struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
unsigned long flags;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
__atlas7_gpio_set_input(a7gc, gpio);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
return 0;
}
@@ -5936,11 +5936,11 @@ static int atlas7_gpio_direction_output(struct gpio_chip *chip,
struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
unsigned long flags;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
__atlas7_gpio_set_output(a7gc, gpio, value);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
return 0;
}
@@ -5956,11 +5956,11 @@ static int atlas7_gpio_get_value(struct gpio_chip *chip,
bank = atlas7_gpio_to_bank(a7gc, gpio);
pin_in_bank = gpio - bank->gpio_offset;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
}
@@ -5978,7 +5978,7 @@ static void atlas7_gpio_set_value(struct gpio_chip *chip,
pin_in_bank = gpio - bank->gpio_offset;
ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
ctrl = readl(ctrl_reg);
if (value)
@@ -5987,7 +5987,7 @@ static void atlas7_gpio_set_value(struct gpio_chip *chip,
ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
writel(ctrl, ctrl_reg);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
}
static const struct of_device_id atlas7_gpio_ids[] = {
@@ -6036,7 +6036,7 @@ static int atlas7_gpio_probe(struct platform_device *pdev)
}
a7gc->nbank = nbank;
- spin_lock_init(&a7gc->lock);
+ raw_spin_lock_init(&a7gc->lock);
/* Setup GPIO Chip */
chip = &a7gc->chip;
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 816015c..793e6f9 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -4,6 +4,7 @@
bool
select PINMUX
select GENERIC_PINCONF
+ select GPIOLIB
config PINCTRL_SUN4I_A10
def_bool MACH_SUN4I
@@ -48,8 +49,8 @@
select PINCTRL_SUNXI
config PINCTRL_SUN8I_H3_R
- def_bool MACH_SUN8I
- select PINCTRL_SUNXI_COMMON
+ def_bool MACH_SUN8I || (ARM64 && ARCH_SUNXI)
+ select PINCTRL_SUNXI
config PINCTRL_SUN8I_V3S
def_bool MACH_SUN8I
@@ -65,11 +66,15 @@
select PINCTRL_SUNXI
config PINCTRL_SUN50I_A64
- bool
+ def_bool ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A64_R
+ def_bool ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
config PINCTRL_SUN50I_H5
- bool
+ def_bool ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 04ccb88..df4ccd6 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -11,6 +11,7 @@
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
+obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
new file mode 100644
index 0000000..e69c8da
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
@@ -0,0 +1,125 @@
+/*
+ * Allwinner A64 SoCs special pins pinctrl driver.
+ *
+ * Based on pinctrl-sun8i-a23-r.c
+ *
+ * Copyright (C) 2016 Icenowy Zheng
+ * Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Copyright (C) 2014 Chen-Yu Tsai
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * Copyright (C) 2014 Boris Brezillon
+ * Boris Brezillon <boris.brezillon@free-electrons.com>
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
+ SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_pwm"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_cir_rx"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */
+};
+
+static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = {
+ .pins = sun50i_a64_r_pins,
+ .npins = ARRAY_SIZE(sun50i_a64_r_pins),
+ .pin_base = PL_BASE,
+ .irq_banks = 1,
+};
+
+static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &sun50i_a64_r_pinctrl_data);
+}
+
+static const struct of_device_id sun50i_a64_r_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-a64-r-pinctrl", },
+ {}
+};
+
+static struct platform_driver sun50i_a64_r_pinctrl_driver = {
+ .probe = sun50i_a64_r_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-a64-r-pinctrl",
+ .of_match_table = sun50i_a64_r_pinctrl_match,
+ },
+};
+builtin_platform_driver(sun50i_a64_r_pinctrl_driver);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 60e6e36..58774ac 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -581,11 +581,11 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
return -ENOTSUPP;
}
- spin_lock_irqsave(&pctl->lock, flags);
+ raw_spin_lock_irqsave(&pctl->lock, flags);
reg = readl(pctl->membase + offset);
reg &= ~(mask << shift);
writel(reg | val << shift, pctl->membase + offset);
- spin_unlock_irqrestore(&pctl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
} /* for each config */
return 0;
@@ -634,7 +634,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
unsigned long flags;
u32 val, mask;
- spin_lock_irqsave(&pctl->lock, flags);
+ raw_spin_lock_irqsave(&pctl->lock, flags);
pin -= pctl->desc->pin_base;
val = readl(pctl->membase + sunxi_mux_reg(pin));
@@ -642,7 +642,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
writel((val & ~mask) | config << sunxi_mux_offset(pin),
pctl->membase + sunxi_mux_reg(pin));
- spin_unlock_irqrestore(&pctl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
@@ -733,7 +733,7 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
unsigned long flags;
u32 regval;
- spin_lock_irqsave(&pctl->lock, flags);
+ raw_spin_lock_irqsave(&pctl->lock, flags);
regval = readl(pctl->membase + reg);
@@ -744,7 +744,7 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
writel(regval, pctl->membase + reg);
- spin_unlock_irqrestore(&pctl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
@@ -856,7 +856,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
return -EINVAL;
}
- spin_lock_irqsave(&pctl->lock, flags);
+ raw_spin_lock_irqsave(&pctl->lock, flags);
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
@@ -869,7 +869,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
regval &= ~(IRQ_CFG_IRQ_MASK << index);
writel(regval | (mode << index), pctl->membase + reg);
- spin_unlock_irqrestore(&pctl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
return 0;
}
@@ -893,13 +893,13 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
unsigned long flags;
u32 val;
- spin_lock_irqsave(&pctl->lock, flags);
+ raw_spin_lock_irqsave(&pctl->lock, flags);
/* Mask the IRQ */
val = readl(pctl->membase + reg);
writel(val & ~(1 << idx), pctl->membase + reg);
- spin_unlock_irqrestore(&pctl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
@@ -910,13 +910,13 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
unsigned long flags;
u32 val;
- spin_lock_irqsave(&pctl->lock, flags);
+ raw_spin_lock_irqsave(&pctl->lock, flags);
/* Unmask the IRQ */
val = readl(pctl->membase + reg);
writel(val | (1 << idx), pctl->membase + reg);
- spin_unlock_irqrestore(&pctl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
@@ -1253,7 +1253,7 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
return -ENOMEM;
platform_set_drvdata(pdev, pctl);
- spin_lock_init(&pctl->lock);
+ raw_spin_lock_init(&pctl->lock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pctl->membase = devm_ioremap_resource(&pdev->dev, res);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index e1aedd2..a9d315a 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -134,7 +134,7 @@ struct sunxi_pinctrl {
unsigned ngroups;
int *irq;
unsigned *irq_array;
- spinlock_t lock;
+ raw_spinlock_t lock;
struct pinctrl_dev *pctl_dev;
unsigned long variant;
};
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index e077a9e..e5826ea 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -9,35 +9,35 @@
if PINCTRL_UNIPHIER
config PINCTRL_UNIPHIER_LD4
- tristate "UniPhier PH1-LD4 SoC pinctrl driver"
+ bool "UniPhier LD4 SoC pinctrl driver"
default ARM
config PINCTRL_UNIPHIER_PRO4
- tristate "UniPhier PH1-Pro4 SoC pinctrl driver"
+ bool "UniPhier Pro4 SoC pinctrl driver"
default ARM
config PINCTRL_UNIPHIER_SLD8
- tristate "UniPhier PH1-sLD8 SoC pinctrl driver"
+ bool "UniPhier sLD8 SoC pinctrl driver"
default ARM
config PINCTRL_UNIPHIER_PRO5
- tristate "UniPhier PH1-Pro5 SoC pinctrl driver"
+ bool "UniPhier Pro5 SoC pinctrl driver"
default ARM
config PINCTRL_UNIPHIER_PXS2
- tristate "UniPhier ProXstream2 SoC pinctrl driver"
+ bool "UniPhier PXs2 SoC pinctrl driver"
default ARM
config PINCTRL_UNIPHIER_LD6B
- tristate "UniPhier PH1-LD6b SoC pinctrl driver"
+ bool "UniPhier LD6b SoC pinctrl driver"
default ARM
config PINCTRL_UNIPHIER_LD11
- tristate "UniPhier PH1-LD11 SoC pinctrl driver"
+ bool "UniPhier LD11 SoC pinctrl driver"
default ARM64
config PINCTRL_UNIPHIER_LD20
- tristate "UniPhier PH1-LD20 SoC pinctrl driver"
+ bool "UniPhier LD20 SoC pinctrl driver"
default ARM64
endif
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 546f23c..30dec0e 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -26,11 +27,18 @@
#include "../pinctrl-utils.h"
#include "pinctrl-uniphier.h"
+#define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000
+#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700
+#define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x1800
+#define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900
+#define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980
+#define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00
+#define UNIPHIER_PINCTRL_IECTRL 0x1d00
+
struct uniphier_pinctrl_priv {
struct pinctrl_desc pctldesc;
struct pinctrl_dev *pctldev;
struct regmap *regmap;
- unsigned int regbase;
struct uniphier_pinctrl_socdata *socdata;
};
@@ -171,7 +179,7 @@ static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev,
reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4;
shift = pupdctrl % 32;
- ret = regmap_read(priv->regmap, priv->regbase + reg, &val);
+ ret = regmap_read(priv->regmap, reg, &val);
if (ret)
return ret;
@@ -231,7 +239,7 @@ static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev,
shift = drvctrl % 32;
mask = (1U << width) - 1;
- ret = regmap_read(priv->regmap, priv->regbase + reg, &val);
+ ret = regmap_read(priv->regmap, reg, &val);
if (ret)
return ret;
@@ -252,8 +260,7 @@ static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev,
/* This pin is always input-enabled. */
return 0;
- ret = regmap_read(priv->regmap,
- priv->regbase + UNIPHIER_PINCTRL_IECTRL, &val);
+ ret = regmap_read(priv->regmap, UNIPHIER_PINCTRL_IECTRL, &val);
if (ret)
return ret;
@@ -366,8 +373,7 @@ static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev,
reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4;
shift = pupdctrl % 32;
- return regmap_update_bits(priv->regmap, priv->regbase + reg,
- 1 << shift, val << shift);
+ return regmap_update_bits(priv->regmap, reg, 1 << shift, val << shift);
}
static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev,
@@ -427,7 +433,7 @@ static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev,
shift = drvctrl % 32;
mask = (1U << width) - 1;
- return regmap_update_bits(priv->regmap, priv->regbase + reg,
+ return regmap_update_bits(priv->regmap, reg,
mask << shift, val << shift);
}
@@ -451,7 +457,7 @@ static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev,
if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
return enable ? 0 : -EINVAL;
- reg = priv->regbase + UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4;
+ reg = UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4;
mask = BIT(iectrl % 32);
return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0);
@@ -601,7 +607,7 @@ static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin,
* stored in the offset+4.
*/
for (; reg < reg_end; reg += 4) {
- ret = regmap_update_bits(priv->regmap, priv->regbase + reg,
+ ret = regmap_update_bits(priv->regmap, reg,
mask << shift, muxval << shift);
if (ret)
return ret;
@@ -610,8 +616,7 @@ static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin,
if (load_pinctrl) {
ret = regmap_write(priv->regmap,
- priv->regbase + UNIPHIER_PINCTRL_LOAD_PINMUX,
- 1);
+ UNIPHIER_PINCTRL_LOAD_PINMUX, 1);
if (ret)
return ret;
}
@@ -698,20 +703,9 @@ int uniphier_pinctrl_probe(struct platform_device *pdev,
if (!priv)
return -ENOMEM;
- if (of_device_is_compatible(dev->of_node, "socionext,ph1-ld4-pinctrl") ||
- of_device_is_compatible(dev->of_node, "socionext,ph1-pro4-pinctrl") ||
- of_device_is_compatible(dev->of_node, "socionext,ph1-sld8-pinctrl") ||
- of_device_is_compatible(dev->of_node, "socionext,ph1-pro5-pinctrl") ||
- of_device_is_compatible(dev->of_node, "socionext,proxstream2-pinctrl") ||
- of_device_is_compatible(dev->of_node, "socionext,ph1-ld6b-pinctrl")) {
- /* old binding */
- priv->regmap = syscon_node_to_regmap(dev->of_node);
- } else {
- priv->regbase = 0x1000;
- parent = of_get_parent(dev->of_node);
- priv->regmap = syscon_node_to_regmap(parent);
- of_node_put(parent);
- }
+ parent = of_get_parent(dev->of_node);
+ priv->regmap = syscon_node_to_regmap(parent);
+ of_node_put(parent);
if (IS_ERR(priv->regmap)) {
dev_err(dev, "failed to get regmap\n");
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index 77a0236..18a8b3a 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2016 Socionext Inc.
+ * Copyright (C) 2016-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -14,7 +14,7 @@
*/
#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
@@ -936,7 +936,6 @@ static const struct of_device_id uniphier_ld11_pinctrl_match[] = {
{ .compatible = "socionext,uniphier-ld11-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, uniphier_ld11_pinctrl_match);
static struct platform_driver uniphier_ld11_pinctrl_driver = {
.probe = uniphier_ld11_pinctrl_probe,
@@ -945,8 +944,4 @@ static struct platform_driver uniphier_ld11_pinctrl_driver = {
.of_match_table = uniphier_ld11_pinctrl_match,
},
};
-module_platform_driver(uniphier_ld11_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-LD11 pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver(uniphier_ld11_pinctrl_driver);
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 9668633..c8d18a2 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2016 Socionext Inc.
+ * Copyright (C) 2016-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -14,7 +14,7 @@
*/
#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
@@ -1034,7 +1034,6 @@ static const struct of_device_id uniphier_ld20_pinctrl_match[] = {
{ .compatible = "socionext,uniphier-ld20-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, uniphier_ld20_pinctrl_match);
static struct platform_driver uniphier_ld20_pinctrl_driver = {
.probe = uniphier_ld20_pinctrl_probe,
@@ -1043,8 +1042,4 @@ static struct platform_driver uniphier_ld20_pinctrl_driver = {
.of_match_table = uniphier_ld20_pinctrl_match,
},
};
-module_platform_driver(uniphier_ld20_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-LD20 pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver(uniphier_ld20_pinctrl_driver);
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index 3edfb6f..8f2ad1c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,7 +14,7 @@
*/
#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
@@ -929,10 +930,8 @@ static int uniphier_ld4_pinctrl_probe(struct platform_device *pdev)
static const struct of_device_id uniphier_ld4_pinctrl_match[] = {
{ .compatible = "socionext,uniphier-ld4-pinctrl" },
- { .compatible = "socionext,ph1-ld4-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, uniphier_ld4_pinctrl_match);
static struct platform_driver uniphier_ld4_pinctrl_driver = {
.probe = uniphier_ld4_pinctrl_probe,
@@ -941,8 +940,4 @@ static struct platform_driver uniphier_ld4_pinctrl_driver = {
.of_match_table = uniphier_ld4_pinctrl_match,
},
};
-module_platform_driver(uniphier_ld4_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-LD4 pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver(uniphier_ld4_pinctrl_driver);
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index 708e510..8a0da93 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,7 +14,7 @@
*/
#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
@@ -1290,10 +1291,8 @@ static int uniphier_ld6b_pinctrl_probe(struct platform_device *pdev)
static const struct of_device_id uniphier_ld6b_pinctrl_match[] = {
{ .compatible = "socionext,uniphier-ld6b-pinctrl" },
- { .compatible = "socionext,ph1-ld6b-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, uniphier_ld6b_pinctrl_match);
static struct platform_driver uniphier_ld6b_pinctrl_driver = {
.probe = uniphier_ld6b_pinctrl_probe,
@@ -1302,8 +1301,4 @@ static struct platform_driver uniphier_ld6b_pinctrl_driver = {
.of_match_table = uniphier_ld6b_pinctrl_match,
},
};
-module_platform_driver(uniphier_ld6b_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-LD6b pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver(uniphier_ld6b_pinctrl_driver);
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index c306e84..a433a30 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,7 +14,7 @@
*/
#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
@@ -1600,10 +1601,8 @@ static int uniphier_pro4_pinctrl_probe(struct platform_device *pdev)
static const struct of_device_id uniphier_pro4_pinctrl_match[] = {
{ .compatible = "socionext,uniphier-pro4-pinctrl" },
- { .compatible = "socionext,ph1-pro4-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, uniphier_pro4_pinctrl_match);
static struct platform_driver uniphier_pro4_pinctrl_driver = {
.probe = uniphier_pro4_pinctrl_probe,
@@ -1612,8 +1611,4 @@ static struct platform_driver uniphier_pro4_pinctrl_driver = {
.of_match_table = uniphier_pro4_pinctrl_match,
},
};
-module_platform_driver(uniphier_pro4_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-Pro4 pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver(uniphier_pro4_pinctrl_driver);
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index 55d4a12..04d00c3 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,7 +14,7 @@
*/
#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
@@ -1365,10 +1366,8 @@ static int uniphier_pro5_pinctrl_probe(struct platform_device *pdev)
static const struct of_device_id uniphier_pro5_pinctrl_match[] = {
{ .compatible = "socionext,uniphier-pro5-pinctrl" },
- { .compatible = "socionext,ph1-pro5-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, uniphier_pro5_pinctrl_match);
static struct platform_driver uniphier_pro5_pinctrl_driver = {
.probe = uniphier_pro5_pinctrl_probe,
@@ -1377,8 +1376,4 @@ static struct platform_driver uniphier_pro5_pinctrl_driver = {
.of_match_table = uniphier_pro5_pinctrl_match,
},
};
-module_platform_driver(uniphier_pro5_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-Pro5 pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver(uniphier_pro5_pinctrl_driver);
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index 85ca5e2..53b6b77 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,7 +14,7 @@
*/
#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
@@ -1277,10 +1278,8 @@ static int uniphier_pxs2_pinctrl_probe(struct platform_device *pdev)
static const struct of_device_id uniphier_pxs2_pinctrl_match[] = {
{ .compatible = "socionext,uniphier-pxs2-pinctrl" },
- { .compatible = "socionext,proxstream2-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, uniphier_pxs2_pinctrl_match);
static struct platform_driver uniphier_pxs2_pinctrl_driver = {
.probe = uniphier_pxs2_pinctrl_probe,
@@ -1289,8 +1288,4 @@ static struct platform_driver uniphier_pxs2_pinctrl_driver = {
.of_match_table = uniphier_pxs2_pinctrl_match,
},
};
-module_platform_driver(uniphier_pxs2_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier ProXstream2 pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver(uniphier_pxs2_pinctrl_driver);
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index da689d8..37deaf6 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,7 +14,7 @@
*/
#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
@@ -856,10 +857,8 @@ static int uniphier_sld8_pinctrl_probe(struct platform_device *pdev)
static const struct of_device_id uniphier_sld8_pinctrl_match[] = {
{ .compatible = "socionext,uniphier-sld8-pinctrl" },
- { .compatible = "socionext,ph1-sld8-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, uniphier_sld8_pinctrl_match);
static struct platform_driver uniphier_sld8_pinctrl_driver = {
.probe = uniphier_sld8_pinctrl_probe,
@@ -868,8 +867,4 @@ static struct platform_driver uniphier_sld8_pinctrl_driver = {
.of_match_table = uniphier_sld8_pinctrl_match,
},
};
-module_platform_driver(uniphier_sld8_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-sLD8 pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver(uniphier_sld8_pinctrl_driver);
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 923f36c..6f2f33b 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,14 +23,6 @@
struct platform_device;
-#define UNIPHIER_PINCTRL_PINMUX_BASE 0x0
-#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700
-#define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x800
-#define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x900
-#define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x980
-#define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0xa00
-#define UNIPHIER_PINCTRL_IECTRL 0xd00
-
/* input enable control register bit */
#define UNIPHIER_PIN_IECTRL_SHIFT 0
#define UNIPHIER_PIN_IECTRL_BITS 8