| commit | 3770821fa360525e6c726cd562a2438a0aa5d566 | [log] [tgz] |
|---|---|---|
| author | Xing Zheng <zhengxing@rock-chips.com> | Thu Jun 30 10:18:59 2016 +0800 |
| committer | Heiko Stuebner <heiko@sntech.de> | Fri Jul 01 01:50:17 2016 +0200 |
| tree | ec494e523c723b6a1adbe00d46b2584c3321a897 | |
| parent | 6e3732a2bebc3f08a59d2eafc2aa613b92055e3f [diff] |
clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.
Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Reported-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>