tree f2d180d2fbf0f10a84d38b1bbeaa7413de7a0a3a
parent ead2bfdb85ab311bc3e1c2e55bff207aafaab096
author Adrian Hunter <adrian.hunter@intel.com> 1495786657 +0300
committer Arnaldo Carvalho de Melo <acme@redhat.com> 1498834255 -0300

perf intel-pt: Do not use TSC packets for calculating CPU cycles to TSC

CBR (core-to-bus ratio) packets provide an indication of CPU frequency. A
more accurate measure can be made by counting the cycles (given by CYC
packets) in between other timing packets (either MTC or TSC). Using TSC
packets has at least 2 issues: 1) timing might have stopped (e.g. mwait) or
2) TSC packets within PSB+ might slip past CYC packets. For now, simply do
not use TSC packets for calculating CPU cycles to TSC. That leaves the case
where 2 MTC packets are used, otherwise falling back to the CBR value.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Link: http://lkml.kernel.org/r/1495786658-18063-37-git-send-email-adrian.hunter@intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>