| commit | af2418be63b4e994cfe4b625939d65b9afdfdf6c | [log] [tgz] |
|---|---|---|
| author | Florian Fainelli <florian@openwrt.org> | Tue Jan 14 09:54:40 2014 -0800 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Fri Jan 24 22:39:55 2014 +0100 |
| tree | 1b01cc2cab2f2fa6ed2c8316df447a68e8ff38b9 | |
| parent | a4c0201e2306b12354776158ae91fa7d2129c12f [diff] |
MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift value of 4) instead of the currently configured 32 bytes L1-cache line size. Reported-by: Daniel Gonzalez <dgcbueu@gmail.com> Signed-off-by: Florian Fainelli <florian@openwrt.org>