| commit | d360a687d99577110c181e67ebfb9a1b6fed63a2 | [log] [tgz] |
|---|---|---|
| author | Vladimir Murzin <vladimir.murzin@arm.com> | Mon Jun 12 13:35:52 2017 +0100 |
| committer | Russell King <rmk+kernel@armlinux.org.uk> | Mon Jun 12 15:47:29 2017 +0100 |
| tree | ac764253122a5234c0c229110f0b0b065a2d8f1d | |
| parent | bbeedfda8eee0b17ea16e4e157c596095458676a [diff] |
ARM: 8682/1: V7M: Set cacheid iff DminLine or IminLine is nonzero Cache support is optional feature in M-class cores, thus DminLine or IminLine of Cache Type Register is zero if caches are not implemented, but we check the whole CTR which has other features encoded there. Let's be more precise and check for DminLine and IminLine of CTR before we set cacheid. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>