| commit | 4483521d81684764cb7f2569bf3e4b10d38ef9f7 | [log] [tgz] |
|---|---|---|
| author | Andrew F. Davis <afd@ti.com> | Tue Dec 12 16:43:05 2017 -0600 |
| committer | Mark Brown <broonie@kernel.org> | Wed Dec 13 12:27:31 2017 +0000 |
| tree | 470d92c42596901a92de2a5f4192ba397fc73bac | |
| parent | 7e2a4dc5c1f0875646816c527cad5943cb6d5cc7 [diff] |
ASoC: tlv320aic32x4: Use correct shift definition for DATATYPE bits Setting the DATATYPE bit field requires shifting our value by 6. Setting the J value of the PLL also requires a shift by 6. Currently the code abuses this fact and uses the shift for the PLL register to set the data-type register. Fix this here by using the definition meant for this register. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>