PCI: designware: Simplify dw_pcie_cfg_read/write() interfaces
Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to
split the address into "addr" and "where". The callees assumed "addr" was
32-bit aligned (with zeros in the low two bits) and they used only the low
two bits of "where".
Accept the entire address in "addr" and drop the now-redundant "where"
argument. As an example, this replaces this:
int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
*val = readb(addr + (where & 1));
with this:
int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
*val = readb(addr):
[bhelgaas: changelog, split access size change to separate patch]
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index f9f468d..01095e1 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -454,7 +454,7 @@
int ret;
exynos_pcie_sideband_dbi_r_mode(pp, true);
- ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
+ ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);
exynos_pcie_sideband_dbi_r_mode(pp, false);
return ret;
}
@@ -465,8 +465,7 @@
int ret;
exynos_pcie_sideband_dbi_w_mode(pp, true);
- ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
- where, size, val);
+ ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);
exynos_pcie_sideband_dbi_w_mode(pp, false);
return ret;
}