| /* |
| * SAMSUNG EXYNOS5422 SoC cpu device tree source |
| * |
| * Copyright (c) 2015 Samsung Electronics Co., Ltd. |
| * http://www.samsung.com |
| * |
| * This file provides desired ordering for Exynos5422: CPU[0123] being the A7. |
| * |
| * The Exynos5420, 5422 and 5800 actually share the same CPU configuration |
| * but particular boards choose different booting order. |
| * |
| * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 |
| * booting cluster (big or LITTLE) is chosen by IROM code by reading |
| * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting |
| * from the LITTLE: Cortex-A7. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x100>; |
| clock-frequency = <1000000000>; |
| cci-control-port = <&cci_control0>; |
| }; |
| |
| cpu1: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x101>; |
| clock-frequency = <1000000000>; |
| cci-control-port = <&cci_control0>; |
| }; |
| |
| cpu2: cpu@102 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x102>; |
| clock-frequency = <1000000000>; |
| cci-control-port = <&cci_control0>; |
| }; |
| |
| cpu3: cpu@103 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x103>; |
| clock-frequency = <1000000000>; |
| cci-control-port = <&cci_control0>; |
| }; |
| |
| cpu4: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x0>; |
| clock-frequency = <1800000000>; |
| cci-control-port = <&cci_control1>; |
| }; |
| |
| cpu5: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x1>; |
| clock-frequency = <1800000000>; |
| cci-control-port = <&cci_control1>; |
| }; |
| |
| cpu6: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x2>; |
| clock-frequency = <1800000000>; |
| cci-control-port = <&cci_control1>; |
| }; |
| |
| cpu7: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x3>; |
| clock-frequency = <1800000000>; |
| cci-control-port = <&cci_control1>; |
| }; |
| }; |
| }; |