| commit | 4ff7e3b65c8e1d8062365296b738fd262cfc2e9c | [log] [tgz] |
|---|---|---|
| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | Wed Oct 09 16:12:39 2013 +0300 |
| committer | Paul Walmsley <paul@pwsan.com> | Thu Oct 24 09:07:23 2013 -0600 |
| tree | 68b7dbcd0779ef82842675754ea16fa7929a08fd | |
| parent | 262c2c9d06585fb0ffc84da18e0f747836ce8baf [diff] |
ARM: OMAP3: fix dpll4_m3_ck and dpll4_m4_ck dividers dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits wide. However, only values from 1 to 32 are allowed. This means we have to add a divider tables and list the dividers explicitly. I believe the same issue is there for other dpll4_mx_ck clocks, but as I'm not familiar with them, I didn't touch them. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>