tree ed99b1b09875c65286362cf4f55672a9cc6a22dd
parent 8044449556338fb27b1a03f6b1dbbdbc59e4ebfa
author Thierry Reding <treding@nvidia.com> 1438274827 +0200
committer Thierry Reding <treding@nvidia.com> 1439466476 +0200

drm/tegra: sor: Write correct head state registers

The head state registers are per head, so they must be properly indexed.
This has worked fine so far because all boards with eDP use it as the
primary output, so it is very likely to end up attached to head 0.

Signed-off-by: Thierry Reding <treding@nvidia.com>