Merge "esoc: Check for modem status LOW prior to error handling"
diff --git a/Documentation/devicetree/bindings/arm/msm/mdm-modem.txt b/Documentation/devicetree/bindings/arm/msm/mdm-modem.txt
index 72e279a..f620892 100644
--- a/Documentation/devicetree/bindings/arm/msm/mdm-modem.txt
+++ b/Documentation/devicetree/bindings/arm/msm/mdm-modem.txt
@@ -6,7 +6,7 @@
Required Properties:
- compatible: The bus devices need to be compatible with
- "qcom,ext-mdm9x55", qcom,ext-sdx50m.
+ "qcom,ext-mdm9x55", "qcom,ext-sdx50m", "qcom,ext-sdx55m".
Required named gpio properties:
- qcom,mdm2ap-errfatal-gpio: gpio for the external modem to indicate to the apps processor
diff --git a/Documentation/devicetree/bindings/qdsp/msm-ssc-sensors.txt b/Documentation/devicetree/bindings/qdsp/msm-ssc-sensors.txt
new file mode 100644
index 0000000..a77c0b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/qdsp/msm-ssc-sensors.txt
@@ -0,0 +1,21 @@
+Qualcomm Technologies, Inc. SSC Driver
+
+msm-ssc-sensors driver implements the mechanism that allows to load SLPI firmware images.
+
+Required properties:
+
+ - compatible: This must be "qcom,msm-ssc-sensors".
+
+Optional properties:
+
+ - qcom,firmware-name: SLPI firmware name, must be "slpi" or "slpi_v1" or "slpi_v2"
+ Firmware name is not required, if sensors driver is sharing processor for execution.
+
+
+Example:
+ The following for sdm845.
+
+ qcom,msm-ssc-sensors {
+ compatible = "qcom,msm-ssc-sensors";
+ qcom,firmware-name = "slpi";
+ };
diff --git a/arch/arm64/boot/dts/qcom/kona-sde.dtsi b/arch/arm64/boot/dts/qcom/kona-sde.dtsi
index 511728c..4e463c7 100644
--- a/arch/arm64/boot/dts/qcom/kona-sde.dtsi
+++ b/arch/arm64/boot/dts/qcom/kona-sde.dtsi
@@ -128,8 +128,11 @@
qcom,sde-wb-linewidth = <4096>;
qcom,sde-mixer-blendstages = <0xb>;
qcom,sde-highest-bank-bit = <0x2>;
- qcom,sde-ubwc-version = <0x300>;
+ qcom,sde-ubwc-version = <0x400>;
+ qcom,sde-ubwc-swizzle = <0x6>;
qcom,sde-ubwc-bw-calc-version = <0x1>;
+ qcom,sde-ubwc-static = <0x1>;
+ qcom,sde-macrotile-mode = <0x1>;
qcom,sde-panic-per-pipe;
qcom,sde-has-cdp;
qcom,sde-has-src-split;
diff --git a/arch/arm64/boot/dts/qcom/kona.dtsi b/arch/arm64/boot/dts/qcom/kona.dtsi
index 0e35a4d..96413d3 100644
--- a/arch/arm64/boot/dts/qcom/kona.dtsi
+++ b/arch/arm64/boot/dts/qcom/kona.dtsi
@@ -910,6 +910,25 @@
vdd_parent-supply = <&VDD_MMCX_LEVEL>;
};
+ spmi_bus: qcom,spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0xc440000 0x1100>,
+ <0xc600000 0x2000000>,
+ <0xe600000 0x100000>,
+ <0xe700000 0xa0000>,
+ <0xc40a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d87000 0xe00>; /* PHY regs */
reg-names = "phy_mem";
@@ -1495,6 +1514,58 @@
dma-coherent;
};
};
+
+ qcom,ssc@5c00000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x5c00000 0x4000>;
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+
+ qcom,proxy-reg-names = "vdd_cx", "vdd_mx";
+ qcom,keep-proxy-regs-on;
+
+ clocks = <&clock_rpmh RPMH_CXO_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ qcom,pas-id = <12>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <424>;
+ qcom,sysmon-id = <3>;
+ qcom,ssctl-instance-id = <0x16>;
+ qcom,firmware-name = "slpi";
+ status = "ok";
+ memory-region = <&pil_slpi_mem>;
+ qcom,complete-ramdump;
+
+ /* Inputs from ssc */
+ interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
+ <&dsps_smp2p_in 0 0>,
+ <&dsps_smp2p_in 2 0>,
+ <&dsps_smp2p_in 1 0>,
+ <&dsps_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Outputs to ssc */
+ qcom,smem-states = <&dsps_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ mbox-names = "slpi-pil";
+ };
+
+ ssc_sensors: qcom,msm-ssc-sensors {
+ compatible = "qcom,msm-ssc-sensors";
+ status = "ok";
+ qcom,firmware-name = "slpi";
+ };
};
#include "kona-bus.dtsi"
diff --git a/arch/arm64/configs/vendor/kona-perf_defconfig b/arch/arm64/configs/vendor/kona-perf_defconfig
index d42bdaa..cfed51d 100644
--- a/arch/arm64/configs/vendor/kona-perf_defconfig
+++ b/arch/arm64/configs/vendor/kona-perf_defconfig
@@ -213,6 +213,7 @@
CONFIG_RFKILL=y
CONFIG_FW_LOADER_USER_HELPER=y
CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y
CONFIG_DMA_CMA=y
CONFIG_MHI_BUS=y
CONFIG_MHI_QCOM=y
@@ -255,6 +256,7 @@
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_INPUT_MISC=y
+CONFIG_INPUT_QPNP_POWER_ON=y
CONFIG_INPUT_UINPUT=y
# CONFIG_SERIO_SERPORT is not set
# CONFIG_VT is not set
@@ -336,6 +338,8 @@
CONFIG_STAGING=y
CONFIG_ASHMEM=y
CONFIG_ION=y
+CONFIG_QPNP_REVID=y
+CONFIG_SPMI_PMIC_CLKDIV=y
CONFIG_MSM_GCC_KONA=y
CONFIG_MSM_VIDEOCC_KONA=y
CONFIG_HWSPINLOCK=y
diff --git a/arch/arm64/configs/vendor/kona_defconfig b/arch/arm64/configs/vendor/kona_defconfig
index 0f45eb51..2f358de 100644
--- a/arch/arm64/configs/vendor/kona_defconfig
+++ b/arch/arm64/configs/vendor/kona_defconfig
@@ -220,6 +220,7 @@
CONFIG_RFKILL=y
CONFIG_FW_LOADER_USER_HELPER=y
CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y
CONFIG_DMA_CMA=y
CONFIG_MHI_BUS=y
CONFIG_MHI_DEBUG=y
@@ -262,6 +263,7 @@
CONFIG_INPUT_JOYSTICK=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_INPUT_MISC=y
+CONFIG_INPUT_QPNP_POWER_ON=y
CONFIG_INPUT_UINPUT=y
# CONFIG_SERIO_SERPORT is not set
# CONFIG_VT is not set
@@ -349,6 +351,8 @@
CONFIG_STAGING=y
CONFIG_ASHMEM=y
CONFIG_ION=y
+CONFIG_QPNP_REVID=y
+CONFIG_SPMI_PMIC_CLKDIV=y
CONFIG_MSM_GCC_KONA=y
CONFIG_MSM_VIDEOCC_KONA=y
CONFIG_HWSPINLOCK=y
diff --git a/drivers/clk/qcom/clk-spmi-pmic-div.c b/drivers/clk/qcom/clk-spmi-pmic-div.c
index c90dfdd..406fbe3 100644
--- a/drivers/clk/qcom/clk-spmi-pmic-div.c
+++ b/drivers/clk/qcom/clk-spmi-pmic-div.c
@@ -1,14 +1,5 @@
-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. */
#include <linux/bitops.h>
#include <linux/clk.h>
@@ -212,6 +203,7 @@ static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
struct regmap *regmap;
struct device *dev = &pdev->dev;
struct device_node *of_node = dev->of_node;
+ bool use_dt_name = false;
const char *parent_name;
int nclks, i, ret, cxo_hz;
char name[20];
@@ -253,6 +245,10 @@ static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
}
cxo_hz = clk_get_rate(cxo);
clk_put(cxo);
+ if (cxo_hz <= 0) {
+ dev_err(dev, "invalid CXO rate: %d\n", cxo_hz);
+ return -EINVAL;
+ }
parent_name = of_clk_get_parent_name(of_node, 0);
if (!parent_name) {
@@ -260,13 +256,26 @@ static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
return -ENODEV;
}
+ if (of_find_property(of_node, "clock-output-names", NULL))
+ use_dt_name = true;
+
init.name = name;
init.parent_names = &parent_name;
init.num_parents = 1;
init.ops = &clk_spmi_pmic_div_ops;
for (i = 0, clkdiv = cc->clks; i < nclks; i++) {
- snprintf(name, sizeof(name), "div_clk%d", i + 1);
+ if (use_dt_name) {
+ ret = of_property_read_string_index(of_node,
+ "clock-output-names", i, &init.name);
+ if (ret) {
+ dev_err(dev, "could not read clock-output-names %d, ret=%d\n",
+ i, ret);
+ return ret;
+ }
+ } else {
+ snprintf(name, sizeof(name), "div_clk%d", i + 1);
+ }
spin_lock_init(&clkdiv[i].lock);
clkdiv[i].base = start + i * 0x100;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index 185cbee..3eba7b0 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -100,12 +100,15 @@ enum {
SDE_HW_UBWC_VER_10 = SDE_HW_UBWC_VER(0x100),
SDE_HW_UBWC_VER_20 = SDE_HW_UBWC_VER(0x200),
SDE_HW_UBWC_VER_30 = SDE_HW_UBWC_VER(0x300),
+ SDE_HW_UBWC_VER_40 = SDE_HW_UBWC_VER(0x400),
};
#define IS_UBWC_20_SUPPORTED(rev) \
IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_20)
#define IS_UBWC_30_SUPPORTED(rev) \
IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_30)
+#define IS_UBWC_40_SUPPORTED(rev) \
+ IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_40)
/**
* Supported SSPP system cache settings
@@ -467,10 +470,14 @@ struct sde_src_blk {
* struct sde_scaler_blk: Scaler information
* @info: HW register and features supported by this sub-blk
* @version: qseed block revision
+ * @h_preload: horizontal preload
+ * @v_preload: vertical preload
*/
struct sde_scaler_blk {
SDE_HW_SUBBLK_INFO;
u32 version;
+ u32 h_preload;
+ u32 v_preload;
};
struct sde_csc_blk {
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
index 4e92618..d6dceed 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
@@ -2412,7 +2412,8 @@ static int reg_dmav1_setup_scaler3_de(struct sde_reg_dma_setup_ops_cfg *buf,
de_config[1] = ((de_cfg->limit & 0xF) << 9) |
((de_cfg->prec_shift & 0x7) << 13) |
- ((de_cfg->clip & 0x7) << 16);
+ ((de_cfg->clip & 0x7) << 16) |
+ ((de_cfg->blend & 0xF) << 20);
de_config[2] = (de_cfg->thr_quiet & 0xFF) |
((de_cfg->thr_dieout & 0x3FF) << 16);
@@ -2500,6 +2501,7 @@ void reg_dmav1_setup_vig_qseed3(struct sde_hw_pipe *ctx,
op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
+ op_mode |= (scaler3_cfg->dyn_exp_disabled) ? BIT(13) : 0;
preload =
((scaler3_cfg->preload_x[0] & 0x7F) << 0) |
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
index 717fc0b..080cce3 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
@@ -332,7 +332,10 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx,
SDE_REG_WRITE(c, SSPP_FETCH_CONFIG,
SDE_FETCH_CONFIG_RESET_VALUE |
ctx->mdp->highest_bank_bit << 18);
- if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version)) {
+ if (IS_UBWC_40_SUPPORTED(ctx->catalog->ubwc_version)) {
+ SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ SDE_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
+ } else if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version)) {
alpha_en_mask = const_alpha_en ? BIT(31) : 0;
SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
alpha_en_mask | (ctx->mdp->ubwc_swizzle) |
@@ -1218,8 +1221,8 @@ struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx,
hw_pipe->cap->perf_features);
if (hw_pipe->ops.get_scaler_ver) {
- hw_pipe->cap->sblk->scaler_blk.version =
- hw_pipe->ops.get_scaler_ver(hw_pipe);
+ sde_init_scaler_blk(&hw_pipe->cap->sblk->scaler_blk,
+ hw_pipe->ops.get_scaler_ver(hw_pipe));
}
rc = sde_hw_blk_init(&hw_pipe->base, SDE_HW_BLK_SSPP, idx, &sde_hw_ops);
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_top.c b/drivers/gpu/drm/msm/sde/sde_hw_top.c
index 738b1bc..82d2476 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_top.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_top.c
@@ -12,6 +12,8 @@
#define SSPP_SPARE 0x28
#define UBWC_DEC_HW_VERSION 0x058
#define UBWC_STATIC 0x144
+#define UBWC_CTRL_2 0x150
+#define UBWC_PREDICTION_MODE 0x154
#define FLD_SPLIT_DISPLAY_CMD BIT(1)
#define FLD_SMART_PANEL_FREE_RUN BIT(2)
@@ -377,7 +379,23 @@ void sde_hw_reset_ubwc(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m)
c.blk_off = 0x0;
ubwc_version = SDE_REG_READ(&c, UBWC_DEC_HW_VERSION);
- if (IS_UBWC_20_SUPPORTED(ubwc_version)) {
+ if (IS_UBWC_40_SUPPORTED(ubwc_version)) {
+ u32 ver = 2;
+ u32 mode = 1;
+ u32 reg = (m->mdp[0].ubwc_swizzle & 0x7) |
+ ((m->mdp[0].ubwc_static & 0x1) << 3) |
+ ((m->mdp[0].highest_bank_bit & 0x7) << 4) |
+ ((m->macrotile_mode & 0x1) << 12);
+
+ if (IS_UBWC_30_SUPPORTED(m->ubwc_version)) {
+ ver = 1;
+ mode = 0;
+ }
+
+ SDE_REG_WRITE(&c, UBWC_STATIC, reg);
+ SDE_REG_WRITE(&c, UBWC_CTRL_2, ver);
+ SDE_REG_WRITE(&c, UBWC_PREDICTION_MODE, mode);
+ } else if (IS_UBWC_20_SUPPORTED(ubwc_version)) {
SDE_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static);
} else if (IS_UBWC_30_SUPPORTED(ubwc_version)) {
u32 reg = m->mdp[0].ubwc_static |
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_util.c b/drivers/gpu/drm/msm/sde/sde_hw_util.c
index a0131ed..ef16644 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_util.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_util.c
@@ -54,6 +54,11 @@ static u32 sde_hw_util_log_mask = SDE_DBG_MASK_NONE;
#define QSEED3L_COEF_LUT_UV_SEP_BIT 5
#define QSEED3L_DIR_FILTER_WEIGHT 0x60
#define QSEED3LITE_SCALER_VERSION 0x2004
+#define QSEED4_SCALER_VERSION 0x3000
+
+#define QSEED3_DEFAULT_PRELOAD_V 0x3
+#define QSEED3_DEFAULT_PRELOAD_H 0x4
+#define QSEED4_DEFAULT_PRELOAD_H 0x5
typedef void (*scaler_lut_type)(struct sde_hw_blk_reg_map *,
struct sde_hw_scaler3_cfg *, u32);
@@ -80,6 +85,17 @@ u32 *sde_hw_util_get_log_mask_ptr(void)
return &sde_hw_util_log_mask;
}
+void sde_init_scaler_blk(struct sde_scaler_blk *blk, u32 version)
+{
+ if (!blk)
+ return;
+
+ blk->version = version;
+ blk->v_preload = QSEED3_DEFAULT_PRELOAD_V;
+ blk->h_preload = QSEED4_DEFAULT_PRELOAD_H;
+ if (version < QSEED4_SCALER_VERSION)
+ blk->h_preload = QSEED3_DEFAULT_PRELOAD_H;
+}
void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg,
const struct sde_drm_scaler_v2 *scale_v2)
{
@@ -116,7 +132,7 @@ void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg,
cfg->uv_sep_lut_idx = scale_v2->uv_sep_lut_idx;
cfg->de.prec_shift = scale_v2->de.prec_shift;
cfg->dir_weight = scale_v2->dir_weight;
- cfg->unsharp_mask_blend = scale_v2->unsharp_mask_blend;
+ cfg->dyn_exp_disabled = (scale_v2->flags & SDE_DYN_EXP_DISABLE) ? 1 : 0;
cfg->de.enable = scale_v2->de.enable;
cfg->de.sharpen_level1 = scale_v2->de.sharpen_level1;
@@ -127,6 +143,7 @@ void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg,
cfg->de.thr_dieout = scale_v2->de.thr_dieout;
cfg->de.thr_low = scale_v2->de.thr_low;
cfg->de.thr_high = scale_v2->de.thr_high;
+ cfg->de.blend = scale_v2->de_blend;
for (i = 0; i < SDE_MAX_DE_CURVES; i++) {
cfg->de.adjust_a[i] = scale_v2->de.adjust_a[i];
@@ -273,7 +290,8 @@ static void _sde_hw_setup_scaler3_de(struct sde_hw_blk_reg_map *c,
sharp_ctl = ((de_cfg->limit & 0xF) << 9) |
((de_cfg->prec_shift & 0x7) << 13) |
- ((de_cfg->clip & 0x7) << 16);
+ ((de_cfg->clip & 0x7) << 16) |
+ ((de_cfg->blend & 0xF) << 20);
shape_ctl = (de_cfg->thr_quiet & 0xFF) |
((de_cfg->thr_dieout & 0x3FF) << 16);
@@ -306,19 +324,14 @@ static void _sde_hw_setup_scaler3_de(struct sde_hw_blk_reg_map *c,
static inline scaler_lut_type get_scaler_lut(
struct sde_hw_scaler3_cfg *scaler3_cfg, u32 scaler_version)
{
- scaler_lut_type lut_ptr = NULL;
+ scaler_lut_type lut_ptr = _sde_hw_setup_scaler3lite_lut;
if (!(scaler3_cfg->lut_flag))
return NULL;
- switch (scaler_version) {
-
- case QSEED3LITE_SCALER_VERSION:
- lut_ptr = _sde_hw_setup_scaler3lite_lut;
- break;
- default:
+ if (scaler_version < QSEED3LITE_SCALER_VERSION)
lut_ptr = _sde_hw_setup_scaler3_lut;
- }
+
return lut_ptr;
}
@@ -343,6 +356,7 @@ void sde_hw_setup_scaler3(struct sde_hw_blk_reg_map *c,
op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
+ op_mode |= (scaler3_cfg->dyn_exp_disabled) ? BIT(13) : 0;
preload =
((scaler3_cfg->preload_x[0] & 0x7F) << 0) |
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_util.h b/drivers/gpu/drm/msm/sde/sde_hw_util.h
index 8008c6c..ef7042f 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_util.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_util.h
@@ -48,6 +48,7 @@ struct sde_hw_blk_reg_map {
* @ adjust_a: A-coefficients for mapping curve
* @ adjust_b: B-coefficients for mapping curve
* @ adjust_c: C-coefficients for mapping curve
+ * @ blend: Unsharp Blend Filter Ratio
*/
struct sde_hw_scaler3_de_cfg {
u32 enable;
@@ -63,6 +64,7 @@ struct sde_hw_scaler3_de_cfg {
int16_t adjust_a[SDE_MAX_DE_CURVES];
int16_t adjust_b[SDE_MAX_DE_CURVES];
int16_t adjust_c[SDE_MAX_DE_CURVES];
+ uint32_t blend;
};
@@ -101,7 +103,7 @@ struct sde_hw_scaler3_de_cfg {
* @ sep_lut: pointer to separable filter LUT
* @ de: detail enhancer configuration
* @ dir_weight: Directional Weight
- * @ unsharp_mask_blend: Unsharp Blend Filter Ratio
+ * @dyn_exp_disabled: Dynamic expansion disabled
*/
struct sde_hw_scaler3_cfg {
u32 enable;
@@ -143,7 +145,7 @@ struct sde_hw_scaler3_cfg {
*/
struct sde_hw_scaler3_de_cfg de;
uint32_t dir_weight;
- uint32_t unsharp_mask_blend;
+ uint32_t dyn_exp_disabled;
};
struct sde_hw_scaler3_lut_cfg {
@@ -175,6 +177,8 @@ int sde_reg_read(struct sde_hw_blk_reg_map *c, u32 reg_off);
void *sde_hw_util_get_dir(void);
+void sde_init_scaler_blk(struct sde_scaler_blk *blk, u32 version);
+
void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg,
const struct sde_drm_scaler_v2 *scale_v2);
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index b94e552..66502c1 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -67,8 +67,7 @@ enum {
R_MAX
};
-#define SDE_QSEED3_DEFAULT_PRELOAD_H 0x4
-#define SDE_QSEED3_DEFAULT_PRELOAD_V 0x3
+#define SDE_QSEED_DEFAULT_DYN_EXP 0x0
#define DEFAULT_REFRESH_RATE 60
@@ -1035,8 +1034,8 @@ static void _sde_plane_setup_scaler3(struct sde_plane *psde,
scale_cfg->src_width[i] /= chroma_subsmpl_h;
scale_cfg->src_height[i] /= chroma_subsmpl_v;
}
- scale_cfg->preload_x[i] = SDE_QSEED3_DEFAULT_PRELOAD_H;
- scale_cfg->preload_y[i] = SDE_QSEED3_DEFAULT_PRELOAD_V;
+ scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
+ scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
/* For pixel extension we need the pre-rotated orientation */
if (pstate->rotation & DRM_MODE_ROTATE_90) {
@@ -1070,6 +1069,7 @@ static void _sde_plane_setup_scaler3(struct sde_plane *psde,
scale_cfg->lut_flag = 0;
scale_cfg->blend_cfg = 1;
scale_cfg->enable = 1;
+ scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
}
/**
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 1678bf5..94a5b4b 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2797,11 +2797,11 @@ static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
const struct dwc3_event_depevt *event, int status)
{
struct dwc3_request *req;
- struct dwc3_request *tmp;
- list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
+ while (!list_empty(&dep->started_list)) {
int ret;
+ req = next_request(&dep->started_list);
ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
req, status);
if (ret)
diff --git a/include/uapi/drm/sde_drm.h b/include/uapi/drm/sde_drm.h
index 670a03b..e55fad3 100644
--- a/include/uapi/drm/sde_drm.h
+++ b/include/uapi/drm/sde_drm.h
@@ -217,6 +217,16 @@ struct sde_drm_de_v1 {
int16_t adjust_c[SDE_MAX_DE_CURVES];
};
+/*
+ * Scaler configuration flags
+ */
+
+/* Disable dynamic expansion */
+#define SDE_DYN_EXP_DISABLE 0x1
+
+#define SDE_DRM_QSEED3LITE
+#define SDE_DRM_QSEED4
+
/**
* struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler
* @enable: Scaler enable
@@ -247,8 +257,9 @@ struct sde_drm_de_v1 {
* @de: Detail enhancer settings
* @dir_weight: Directional Weight
* @unsharp_mask_blend: Unsharp Blend Filter Ratio
+ * @de_blend: Ratio of two unsharp mask filters
+ * @flags: Scaler configuration flags
*/
-#define SDE_DRM_QSEED3LITE
struct sde_drm_scaler_v2 {
/*
* General definitions
@@ -303,6 +314,8 @@ struct sde_drm_scaler_v2 {
struct sde_drm_de_v1 de;
uint32_t dir_weight;
uint32_t unsharp_mask_blend;
+ uint32_t de_blend;
+ uint32_t flags;
};
/* Number of dest scalers supported */