| /* |
| * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC |
| * |
| * Copyright (C) 2015, Applied Micro Circuits Corporation |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| */ |
| |
| / { |
| compatible = "apm,xgene-shadowcat"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu@000 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x000>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@001 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x001>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@100 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x100>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@101 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x101>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@200 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x200>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@201 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x201>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@300 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x300>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@301 { |
| device_type = "cpu"; |
| compatible = "apm,strega", "arm,armv8"; |
| reg = <0x0 0x301>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| }; |
| |
| gic: interrupt-controller@78090000 { |
| compatible = "arm,cortex-a15-gic"; |
| #interrupt-cells = <3>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| interrupt-controller; |
| interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ |
| ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */ |
| reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ |
| <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */ |
| <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */ |
| <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */ |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <1 12 0xff04>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 0 0xff04>, /* Secure Phys IRQ */ |
| <1 13 0xff04>, /* Non-secure Phys IRQ */ |
| <1 14 0xff04>, /* Virt IRQ */ |
| <1 15 0xff04>; /* Hyp IRQ */ |
| clock-frequency = <50000000>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| clocks { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| refclk: refclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <1>; |
| clock-frequency = <100000000>; |
| clock-output-names = "refclk"; |
| }; |
| |
| socpll: socpll@17000120 { |
| compatible = "apm,xgene-socpll-clock"; |
| #clock-cells = <1>; |
| clocks = <&refclk 0>; |
| reg = <0x0 0x17000120 0x0 0x1000>; |
| clock-output-names = "socpll"; |
| }; |
| |
| socplldiv2: socplldiv2 { |
| compatible = "fixed-factor-clock"; |
| #clock-cells = <1>; |
| clocks = <&socpll 0>; |
| clock-mult = <1>; |
| clock-div = <2>; |
| clock-output-names = "socplldiv2"; |
| }; |
| |
| pcie0clk: pcie0clk@1f2bc000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f2bc000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| clock-output-names = "pcie0clk"; |
| }; |
| |
| xge0clk: xge0clk@1f61c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f61c000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| enable-mask = <0x3>; |
| csr-mask = <0x3>; |
| clock-output-names = "xge0clk"; |
| }; |
| |
| xge1clk: xge1clk@1f62c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f62c000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| enable-mask = <0x3>; |
| csr-mask = <0x3>; |
| clock-output-names = "xge1clk"; |
| }; |
| }; |
| |
| scu: system-clk-controller@17000000 { |
| compatible = "apm,xgene-scu","syscon"; |
| reg = <0x0 0x17000000 0x0 0x400>; |
| }; |
| |
| reboot: reboot@17000014 { |
| compatible = "syscon-reboot"; |
| regmap = <&scu>; |
| offset = <0x14>; |
| mask = <0x1>; |
| }; |
| |
| serial0: serial@10600000 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0 0x10600000 0x0 0x1000>; |
| reg-shift = <2>; |
| clock-frequency = <10000000>; |
| interrupt-parent = <&gic>; |
| interrupts = <0x0 0x4c 0x4>; |
| }; |
| |
| sata1: sata@1a000000 { |
| compatible = "apm,xgene-ahci"; |
| reg = <0x0 0x1a000000 0x0 0x1000>, |
| <0x0 0x1f200000 0x0 0x1000>, |
| <0x0 0x1f20d000 0x0 0x1000>, |
| <0x0 0x1f20e000 0x0 0x1000>; |
| interrupts = <0x0 0x5a 0x4>; |
| dma-coherent; |
| }; |
| |
| sata2: sata@1a200000 { |
| compatible = "apm,xgene-ahci"; |
| reg = <0x0 0x1a200000 0x0 0x1000>, |
| <0x0 0x1f210000 0x0 0x1000>, |
| <0x0 0x1f21d000 0x0 0x1000>, |
| <0x0 0x1f21e000 0x0 0x1000>; |
| interrupts = <0x0 0x5b 0x4>; |
| dma-coherent; |
| }; |
| |
| sata3: sata@1a400000 { |
| compatible = "apm,xgene-ahci"; |
| reg = <0x0 0x1a400000 0x0 0x1000>, |
| <0x0 0x1f220000 0x0 0x1000>, |
| <0x0 0x1f22d000 0x0 0x1000>, |
| <0x0 0x1f22e000 0x0 0x1000>; |
| interrupts = <0x0 0x5c 0x4>; |
| dma-coherent; |
| }; |
| |
| sbgpio: sbgpio@17001000{ |
| compatible = "apm,xgene-gpio-sb"; |
| reg = <0x0 0x17001000 0x0 0x400>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupts = <0x0 0x28 0x1>, |
| <0x0 0x29 0x1>, |
| <0x0 0x2a 0x1>, |
| <0x0 0x2b 0x1>, |
| <0x0 0x2c 0x1>, |
| <0x0 0x2d 0x1>, |
| <0x0 0x2e 0x1>, |
| <0x0 0x2f 0x1>; |
| }; |
| |
| sgenet0: ethernet@1f610000 { |
| compatible = "apm,xgene2-sgenet"; |
| status = "disabled"; |
| reg = <0x0 0x1f610000 0x0 0x10000>, |
| <0x0 0x1f600000 0x0 0Xd100>, |
| <0x0 0x20000000 0x0 0X20000>; |
| interrupts = <0 96 4>, |
| <0 97 4>; |
| dma-coherent; |
| clocks = <&xge0clk 0>; |
| local-mac-address = [00 01 73 00 00 01]; |
| phy-connection-type = "sgmii"; |
| }; |
| |
| xgenet1: ethernet@1f620000 { |
| compatible = "apm,xgene2-xgenet"; |
| status = "disabled"; |
| reg = <0x0 0x1f620000 0x0 0x10000>, |
| <0x0 0x1f600000 0x0 0Xd100>, |
| <0x0 0x20000000 0x0 0X220000>; |
| interrupts = <0 108 4>, |
| <0 109 4>; |
| port-id = <1>; |
| dma-coherent; |
| clocks = <&xge1clk 0>; |
| local-mac-address = [00 01 73 00 00 02]; |
| phy-connection-type = "xgmii"; |
| }; |
| }; |
| }; |