tree 133061595c50da263866003aca05cdccacc46576
parent 6ce4eac1f600b34f2f7f58f9cd8f0503d79e42ae
author Ludovic Desroches <ludovic.desroches@atmel.com> 1385136523 +0100
committer Nicolas Ferre <nicolas.ferre@atmel.com> 1385990082 +0100

ARM: at91: sama5d3: reduce TWI internal clock frequency

With some devices, transfer hangs during I2C frame transmission. This issue
disappears when reducing the internal frequency of the TWI IP. Even if it is
indicated that internal clock max frequency is 66MHz, it seems we have
oversampling on I2C signals making TWI believe that a transfer in progress
is done.

This fix has no impact on the I2C bus frequency.

Cc: <stable@vger.kernel.org> #3.10+
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>