tree 26e82f80645bce9b6eec9db18d219c736fbc925a
parent 28d6f93d201d20ce47a9e8414655569a78f0353c
author Markos Chandras <markos.chandras@imgtec.com> 1417513579 +0000
committer Markos Chandras <markos.chandras@imgtec.com> 1424187456 +0000

MIPS: Add LLB bit and related feature for the Config 5 CP0 register

The LLBIT (bit 4) in the Config5 CP0 register indicates the software
availability of the Load-Linked bit. This bit is only set by hardware
and it has the following meaning:

0: LLB functionality is not supported
1: LLB functionality is supported. The following feature are also
supported:

- ERETNC instruction. Similar to ERET but it does not clear the LLB
bit in the LLAddr register.
- CP0 LLAddr/LLB bit must be set
- LLbit is software accessible through the LLAddr[0]

This will be used later on to emulate R2 LL/SC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>