| commit | 5d6f7ea752228788eddce0b9e268fa1f0eabdd7f | [log] [tgz] |
|---|---|---|
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | Sat Jun 28 02:04:08 2014 +0300 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Fri Aug 08 17:43:28 2014 +0200 |
| tree | 2fa7b87dc26a81281bdbc9bf24a190e3f915eb1f | |
| parent | 4811ff4f2388727a161ea49c2b0ddca95e44c7f9 [diff] |
drm/i915: Add chv cmnlane power wells CHV has two display PHYs so there are also two cmnlane power wells. Add the approriate code to power the wells up/down. Like on VLV we do the cmnreset assert/deassert and the DPLL refclock enabling at approriate times. This code actually works on my bsw. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>