| commit | 603a0c8af9cb23f7cf94d57e76113fef51848200 | [log] [tgz] |
|---|---|---|
| author | Mylène Josserand <mylene.josserand@free-electrons.com> | Tue Jan 17 15:02:22 2017 +0100 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Tue Jan 17 17:42:46 2017 +0100 |
| tree | 0fb26415f874bacf728d62db4c55209ff6c3d254 | |
| parent | 70421257c068b91476e70cade15fca68045d0693 [diff] |
clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig The audio DAI needs to set the clock rates of the ac-dig clock. To make it possible, the parent PLL audio clock rates should also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>