tree 46b597f444fb8aecec8647da2eea4fdf805e6d65
parent a3564d2b5236b73bceb271f482965d38cd9d8d8e
author Ben Widawsky <benjamin.widawsky@intel.com> 1386897963 -0800
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1386953484 +0100

drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent

I stumbled on to some unimplemented errata. To be honest, I am not
really sure of the impact, just that the docs say to do.

No w/a name for this one.

v2: v1 was a stale thing which should have never seen the light of day.
(Haihao)

Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>