| commit | 63c3194b82530bd71fd49db84eb7ab656b8d404a | [log] [tgz] |
|---|---|---|
| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | Fri Dec 23 11:21:10 2016 +0200 |
| committer | Mark Brown <broonie@kernel.org> | Sat Dec 31 18:43:11 2016 +0000 |
| tree | c21e4e4467dc29598477b248a2aecdb5374174e0 | |
| parent | a5de5b74a50113564a1e0850e2da96c37c35e55d [diff] |
ASoC: tlv320aic3x: Mark the RESET register as volatile The RESET register only have one self clearing bit and it should not be cached. If it is cached, when we sync the registers back to the chip we will initiate a software reset as well, which is not desirable. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: Mark Brown <broonie@kernel.org>