tree cd2e48fa02b4982784ad5cf7c09bd0eb90fc06c8
parent 699b477a0d3a5bc68034a1520a4337ea0a20f63b
author Thierry Reding <treding@nvidia.com> 1427388236 +0100
committer Thierry Reding <treding@nvidia.com> 1428674660 +0200

clk: tegra: Model oscillator as clock

Currently the Tegra clock driver simplifies the clock tree somewhat by
taking advantage of the fact that clk_m runs at the same frequency as
the oscillator. While that's true on all currently supported SoCs, it
does not apply to Tegra210 anymore. On Tegra210 clk_m is typically
divided down from the oscillator frequency. To support that setup, add
a separate clock for the oscillator that both clk_m and pll_ref derive
from.

Modify the tegra_osc_clk_init() function to take an additional divider
parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210
will read the divider from a register in the clock & reset controller.

Signed-off-by: Thierry Reding <treding@nvidia.com>