cpufreq for freescale mx51
Currently, only two operating points: 160Mhz and 800Mhz.
the operating points are tested on babbage 3.0
Signed-off-by: Yong Shen <yong.shen@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index a790bf2..a42c720 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
@@ -20,6 +20,8 @@
#ifndef __ASM_ARCH_MXC_H__
#define __ASM_ARCH_MXC_H__
+#include <linux/types.h>
+
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
@@ -133,6 +135,15 @@
# define cpu_is_mxc91231() (0)
#endif
+#ifndef __ASSEMBLY__
+
+struct cpu_op {
+ u32 cpu_rate;
+};
+
+extern struct cpu_op *(*get_cpu_op)(int *op);
+#endif
+
#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
/* These are deprecated, use mx[23][157]_setup_weimcs instead. */
#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))