| /* |
| * Device Tree Source for Keystone 2 clock tree |
| * |
| * Copyright (C) 2013 Texas Instruments, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| refclkmain: refclkmain { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <122880000>; |
| clock-output-names = "refclk-main"; |
| }; |
| |
| mainpllclk: mainpllclk@2310110 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,main-pll-clock"; |
| clocks = <&refclkmain>; |
| reg = <0x02620350 4>, <0x02310110 4>; |
| reg-names = "control", "multiplier"; |
| fixed-postdiv = <2>; |
| }; |
| |
| papllclk: papllclk@2620358 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,pll-clock"; |
| clocks = <&refclkmain>; |
| clock-output-names = "pa-pll-clk"; |
| reg = <0x02620358 4>; |
| reg-names = "control"; |
| fixed-postdiv = <6>; |
| }; |
| |
| ddr3allclk: ddr3apllclk@2620360 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,pll-clock"; |
| clocks = <&refclkmain>; |
| clock-output-names = "ddr-3a-pll-clk"; |
| reg = <0x02620360 4>; |
| reg-names = "control"; |
| fixed-postdiv = <6>; |
| }; |
| |
| ddr3bllclk: ddr3bpllclk@2620368 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,pll-clock"; |
| clocks = <&refclkmain>; |
| clock-output-names = "ddr-3b-pll-clk"; |
| reg = <0x02620368 4>; |
| reg-names = "control"; |
| fixed-postdiv = <6>; |
| }; |
| |
| armpllclk: armpllclk@2620370 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,pll-clock"; |
| clocks = <&refclkmain>; |
| clock-output-names = "arm-pll-clk"; |
| reg = <0x02620370 4>; |
| reg-names = "control"; |
| fixed-postdiv = <6>; |
| }; |
| |
| mainmuxclk: mainmuxclk@2310108 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,pll-mux-clock"; |
| clocks = <&mainpllclk>, <&refclkmain>; |
| reg = <0x02310108 4>; |
| bit-shift = <23>; |
| bit-mask = <1>; |
| clock-output-names = "mainmuxclk"; |
| }; |
| |
| chipclk1: chipclk1 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&mainmuxclk>; |
| clock-div = <1>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk1"; |
| }; |
| |
| chipclk1rstiso: chipclk1rstiso { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&mainmuxclk>; |
| clock-div = <1>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk1rstiso"; |
| }; |
| |
| gemtraceclk: gemtraceclk@2310120 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,pll-divider-clock"; |
| clocks = <&mainmuxclk>; |
| reg = <0x02310120 4>; |
| bit-shift = <0>; |
| bit-mask = <8>; |
| clock-output-names = "gemtraceclk"; |
| }; |
| |
| chipstmxptclk: chipstmxptclk { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,pll-divider-clock"; |
| clocks = <&mainmuxclk>; |
| reg = <0x02310164 4>; |
| bit-shift = <0>; |
| bit-mask = <8>; |
| clock-output-names = "chipstmxptclk"; |
| }; |
| |
| chipclk12: chipclk12 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&chipclk1>; |
| clock-div = <2>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk12"; |
| }; |
| |
| chipclk13: chipclk13 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&chipclk1>; |
| clock-div = <3>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk13"; |
| }; |
| |
| chipclk14: chipclk14 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&chipclk1>; |
| clock-div = <4>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk14"; |
| }; |
| |
| chipclk16: chipclk16 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&chipclk1>; |
| clock-div = <6>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk16"; |
| }; |
| |
| chipclk112: chipclk112 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&chipclk1>; |
| clock-div = <12>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk112"; |
| }; |
| |
| chipclk124: chipclk124 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&chipclk1>; |
| clock-div = <24>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk114"; |
| }; |
| |
| chipclk1rstiso13: chipclk1rstiso13 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&chipclk1rstiso>; |
| clock-div = <3>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk1rstiso13"; |
| }; |
| |
| chipclk1rstiso14: chipclk1rstiso14 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&chipclk1rstiso>; |
| clock-div = <4>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk1rstiso14"; |
| }; |
| |
| chipclk1rstiso16: chipclk1rstiso16 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&chipclk1rstiso>; |
| clock-div = <6>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk1rstiso16"; |
| }; |
| |
| chipclk1rstiso112: chipclk1rstiso112 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&chipclk1rstiso>; |
| clock-div = <12>; |
| clock-mult = <1>; |
| clock-output-names = "chipclk1rstiso112"; |
| }; |
| |
| clkmodrst0: clkmodrst0 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk16>; |
| clock-output-names = "modrst0"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| |
| clkusb: clkusb { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk16>; |
| clock-output-names = "usb"; |
| reg = <0x02350008 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clkaemifspi: clkaemifspi { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk16>; |
| clock-output-names = "aemif-spi"; |
| reg = <0x0235000c 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| |
| clkdebugsstrc: clkdebugsstrc { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "debugss-trc"; |
| reg = <0x02350014 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clktetbtrc: clktetbtrc { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "tetb-trc"; |
| reg = <0x02350018 0xb00>, <0x02350004 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <1>; |
| }; |
| |
| clkpa: clkpa { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk16>; |
| clock-output-names = "pa"; |
| reg = <0x0235001c 0xb00>, <0x02350008 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <2>; |
| }; |
| |
| clkcpgmac: clkcpgmac { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkpa>; |
| clock-output-names = "cpgmac"; |
| reg = <0x02350020 0xb00>, <0x02350008 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <2>; |
| }; |
| |
| clksa: clksa { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkpa>; |
| clock-output-names = "sa"; |
| reg = <0x02350024 0xb00>, <0x02350008 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <2>; |
| }; |
| |
| clkpcie: clkpcie { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk12>; |
| clock-output-names = "pcie"; |
| reg = <0x02350028 0xb00>, <0x0235000c 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <3>; |
| }; |
| |
| clksrio: clksrio { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk1rstiso13>; |
| clock-output-names = "srio"; |
| reg = <0x0235002c 0xb00>, <0x02350010 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <4>; |
| }; |
| |
| clkhyperlink0: clkhyperlink0 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk12>; |
| clock-output-names = "hyperlink-0"; |
| reg = <0x02350030 0xb00>, <0x02350014 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <5>; |
| }; |
| |
| clksr: clksr { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk1rstiso112>; |
| clock-output-names = "sr"; |
| reg = <0x02350034 0xb00>, <0x02350018 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <6>; |
| }; |
| |
| clkmsmcsram: clkmsmcsram { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk1>; |
| clock-output-names = "msmcsram"; |
| reg = <0x02350038 0xb00>, <0x0235001c 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <7>; |
| }; |
| |
| clkgem0: clkgem0 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk1>; |
| clock-output-names = "gem0"; |
| reg = <0x0235003c 0xb00>, <0x02350020 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <8>; |
| }; |
| |
| clkgem1: clkgem1 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk1>; |
| clock-output-names = "gem1"; |
| reg = <0x02350040 0xb00>, <0x02350024 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <9>; |
| }; |
| |
| clkgem2: clkgem2 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk1>; |
| clock-output-names = "gem2"; |
| reg = <0x02350044 0xb00>, <0x02350028 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <10>; |
| }; |
| |
| clkgem3: clkgem3 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk1>; |
| clock-output-names = "gem3"; |
| reg = <0x02350048 0xb00>, <0x0235002c 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <11>; |
| }; |
| |
| clkgem4: clkgem4 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk1>; |
| clock-output-names = "gem4"; |
| reg = <0x0235004c 0xb00>, <0x02350030 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <12>; |
| }; |
| |
| clkgem5: clkgem5 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk1>; |
| clock-output-names = "gem5"; |
| reg = <0x02350050 0xb00>, <0x02350034 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <13>; |
| }; |
| |
| clkgem6: clkgem6 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk1>; |
| clock-output-names = "gem6"; |
| reg = <0x02350054 0xb00>, <0x02350038 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <14>; |
| }; |
| |
| clkgem7: clkgem7 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk1>; |
| clock-output-names = "gem7"; |
| reg = <0x02350058 0xb00>, <0x0235003c 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <15>; |
| }; |
| |
| clkddr30: clkddr30 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk12>; |
| clock-output-names = "ddr3-0"; |
| reg = <0x0235005c 0xb00>, <0x02350040 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <16>; |
| }; |
| |
| clkddr31: clkddr31 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "ddr3-1"; |
| reg = <0x02350060 0xb00>, <0x02350040 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <16>; |
| }; |
| |
| clktac: clktac { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "tac"; |
| reg = <0x02350064 0xb00>, <0x02350044 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <17>; |
| }; |
| |
| clkrac01: clktac01 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "rac-01"; |
| reg = <0x02350068 0xb00>, <0x02350044 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <17>; |
| }; |
| |
| clkrac23: clktac23 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "rac-23"; |
| reg = <0x0235006c 0xb00>, <0x02350048 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <18>; |
| }; |
| |
| clkfftc0: clkfftc0 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "fftc-0"; |
| reg = <0x02350070 0xb00>, <0x0235004c 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <19>; |
| }; |
| |
| clkfftc1: clkfftc1 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "fftc-1"; |
| reg = <0x02350074 0xb00>, <0x023504c0 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <19>; |
| }; |
| |
| clkfftc2: clkfftc2 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "fftc-2"; |
| reg = <0x02350078 0xb00>, <0x02350050 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <20>; |
| }; |
| |
| clkfftc3: clkfftc3 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "fftc-3"; |
| reg = <0x0235007c 0xb00>, <0x02350050 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <20>; |
| }; |
| |
| clkfftc4: clkfftc4 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "fftc-4"; |
| reg = <0x02350080 0xb00>, <0x02350050 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <20>; |
| }; |
| |
| clkfftc5: clkfftc5 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "fftc-5"; |
| reg = <0x02350084 0xb00>, <0x02350050 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <20>; |
| }; |
| |
| clkaif: clkaif { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "aif"; |
| reg = <0x02350088 0xb00>, <0x02350054 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <21>; |
| }; |
| |
| clktcp3d0: clktcp3d0 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "tcp3d-0"; |
| reg = <0x0235008c 0xb00>, <0x02350058 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <22>; |
| }; |
| |
| clktcp3d1: clktcp3d1 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "tcp3d-1"; |
| reg = <0x02350090 0xb00>, <0x02350058 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <22>; |
| }; |
| |
| clktcp3d2: clktcp3d2 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "tcp3d-2"; |
| reg = <0x02350094 0xb00>, <0x0235005c 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <23>; |
| }; |
| |
| clktcp3d3: clktcp3d3 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "tcp3d-3"; |
| reg = <0x02350098 0xb00>, <0x0235005c 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <23>; |
| }; |
| |
| clkvcp0: clkvcp0 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "vcp-0"; |
| reg = <0x0235009c 0xb00>, <0x02350060 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <24>; |
| }; |
| |
| clkvcp1: clkvcp1 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "vcp-1"; |
| reg = <0x023500a0 0xb00>, <0x02350060 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <24>; |
| }; |
| |
| clkvcp2: clkvcp2 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "vcp-2"; |
| reg = <0x023500a4 0xb00>, <0x02350060 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <24>; |
| }; |
| |
| clkvcp3: clkvcp3 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "vcp-3"; |
| reg = <0x0235000a8 0xb00>, <0x02350060 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <24>; |
| }; |
| |
| clkvcp4: clkvcp4 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "vcp-4"; |
| reg = <0x023500ac 0xb00>, <0x02350064 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <25>; |
| }; |
| |
| clkvcp5: clkvcp5 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "vcp-5"; |
| reg = <0x023500b0 0xb00>, <0x02350064 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <25>; |
| }; |
| |
| clkvcp6: clkvcp6 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "vcp-6"; |
| reg = <0x023500b4 0xb00>, <0x02350064 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <25>; |
| }; |
| |
| clkvcp7: clkvcp7 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "vcp-7"; |
| reg = <0x023500b8 0xb00>, <0x02350064 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <25>; |
| }; |
| |
| clkbcp: clkbcp { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "bcp"; |
| reg = <0x023500bc 0xb00>, <0x02350068 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <26>; |
| }; |
| |
| clkdxb: clkdxb { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "dxb"; |
| reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <27>; |
| }; |
| |
| clkhyperlink1: clkhyperlink1 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk12>; |
| clock-output-names = "hyperlink-1"; |
| reg = <0x023500c4 0xb00>, <0x02350070 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <28>; |
| }; |
| |
| clkxge: clkxge { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&chipclk13>; |
| clock-output-names = "xge"; |
| reg = <0x023500c8 0xb00>, <0x02350074 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <29>; |
| }; |
| |
| clkwdtimer0: clkwdtimer0 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkmodrst0>; |
| clock-output-names = "timer0"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clkwdtimer1: clkwdtimer1 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkmodrst0>; |
| clock-output-names = "timer1"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clkwdtimer2: clkwdtimer2 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkmodrst0>; |
| clock-output-names = "timer2"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clkwdtimer3: clkwdtimer3 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkmodrst0>; |
| clock-output-names = "timer3"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clkuart0: clkuart0 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkmodrst0>; |
| clock-output-names = "uart0"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clkuart1: clkuart1 { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkmodrst0>; |
| clock-output-names = "uart1"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clkaemif: clkaemif { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkaemifspi>; |
| clock-output-names = "aemif"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clkusim: clkusim { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkmodrst0>; |
| clock-output-names = "usim"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clki2c: clki2c { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkmodrst0>; |
| clock-output-names = "i2c"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clkspi: clkspi { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkaemifspi>; |
| clock-output-names = "spi"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clkgpio: clkgpio { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkmodrst0>; |
| clock-output-names = "gpio"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| |
| clkkeymgr: clkkeymgr { |
| #clock-cells = <0>; |
| compatible = "ti,keystone,psc-clock"; |
| clocks = <&clkmodrst0>; |
| clock-output-names = "keymgr"; |
| reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
| reg-names = "control", "domain"; |
| domain-id = <0>; |
| }; |
| }; |