| commit | 6c7b03e1aef2e92176435f4fa562cc483422d20f | [log] [tgz] |
|---|---|---|
| author | Boris Brezillon <boris.brezillon@free-electrons.com> | Fri Mar 27 23:53:15 2015 +0100 |
| committer | Boris Brezillon <boris.brezillon@free-electrons.com> | Fri Jun 19 14:43:39 2015 +0200 |
| tree | 5630b97e175b6b789e152e43591388b2346ed973 | |
| parent | 03bc10ab5b0f9b8f81bffbe6e40c944f9d3dbcc5 [diff] |
clk: at91: pll: fix input range validity check The PLL impose a certain input range to work correctly, but it appears that this input range does not apply on the input clock (or parent clock) but on the input clock after it has passed the PLL divisor. Fix the implementation accordingly. Cc: <stable@vger.kernel.org> # v3.14+ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reported-by: Jonas Andersson <jonas@microbit.se>