| commit | 7085f5d9e803688045e92ccb69e1f7fe0eee9621 | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Tue Jun 05 19:17:13 2018 +0200 |
| committer | Simon Horman <horms+renesas@verge.net.au> | Mon Jun 25 15:30:27 2018 +0200 |
| tree | 3107fc4f263613165590c9ab912ff328c50493bd | |
| parent | eb614d94395293da7beecaa29555acb8966a2796 [diff] |
arm64: dts: renesas: r8a77990: Add secondary CA53 CPU core Add a device node for the second Cortex-A53 CPU core on the Renesas R-Car E3 (r8a77990) SoC, and adjust the interrupt delivery masks for ARM Generic Interrupt Controller and Architectured Timer. Based on a patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>