clk: samsung: exynos7: Correct CMU_FSYS1 clocks names
This patch renames CMU_FSYS1 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys1_200.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 667faed..acdf2e5 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -63,7 +63,8 @@
#define CLK_SCLK_MMC1 7
#define CLK_SCLK_MMC0 8
#define CLK_ACLK_FSYS0_200 9
-#define TOP1_NR_CLK 10
+#define CLK_ACLK_FSYS1_200 10
+#define TOP1_NR_CLK 11
/* CCORE */
#define PCLK_RTC 1