| commit | 77bdb58795d86262e96ba37524489ba0969de253 | [log] [tgz] |
|---|---|---|
| author | Andrew F. Davis <afd@ti.com> | Tue Dec 12 16:43:06 2017 -0600 |
| committer | Mark Brown <broonie@kernel.org> | Wed Dec 13 12:27:48 2017 +0000 |
| tree | fb0c1a58198d843ffeb98ededc381a969819889f | |
| parent | 4483521d81684764cb7f2569bf3e4b10d38ef9f7 [diff] |
ASoC: tlv320aic32x4: Use correct shift definition for DATALEN bits Setting the DATALEN bit field requires shifting our value by 4. Setting the OSR value of the PLL divider also requires a shift by 4. Currently the code abuses this fact and uses the shift for the divider register to set the data-length register. Fix this here by using the definition meant for this register. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>