| commit | 7c289385b84d136089b8a1149321ebffa5193595 | [log] [tgz] |
|---|---|---|
| author | Russell King <rmk+kernel@arm.linux.org.uk> | Sat Feb 05 10:41:55 2011 +0000 |
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | Mon Feb 07 15:15:26 2011 +0000 |
| tree | 2d591872a86dfa7f042371501d014e54e3ecda50 | |
| parent | ec11594fbd5a3d2a47a7a7eda6d076363b78957c [diff] |
ALSA: AACI: allow writes to MAINCR to take effect The AACI TRM requires the MAINCR enable bit to be held zero for two bitclk cycles plus three apb_pclk cycles. Use a delay of 1us to ensure this. Ensure that writes to MAINCR to change the addressed codec only happen when required, and that they take effect in a similar manner to the above, otherwise we seem to occasionally have stuck slot busy bits. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>