| commit | 7f081f175502373673c015a4d0fa1d5cc264758a | [log] [tgz] |
|---|---|---|
| author | Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> | Tue Oct 08 16:17:48 2013 +0100 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Tue Oct 29 21:18:23 2013 +0100 |
| tree | bd53f2a1470b37b79d7e5f5f6e0fe7bcfbc452d4 | |
| parent | 959f58544b7f20c92d5eb43d1232c96c15c01bfb [diff] |
MIPS: Perf: Fix 74K cache map According to Software User's Manual, the event of last-level-cache read/write misses is mapped to even counters. Odd counters of that event number count miss cycles. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6036/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>