tree bd53f2a1470b37b79d7e5f5f6e0fe7bcfbc452d4
parent 959f58544b7f20c92d5eb43d1232c96c15c01bfb
author Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> 1381245468 +0100
committer Ralf Baechle <ralf@linux-mips.org> 1383077903 +0100

MIPS: Perf: Fix 74K cache map

According to Software User's Manual, the event of last-level-cache
read/write misses is mapped to even counters. Odd counters of that
event number count miss cycles.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6036/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>