| commit | 82aeef0bf03684b377678c00c05e613f30dca39c | [log] [tgz] |
|---|---|---|
| author | Li, Zhen-Hua <zhen-hual@hp.com> | Fri Sep 13 14:27:32 2013 +0800 |
| committer | Joerg Roedel <joro@8bytes.org> | Tue Sep 24 13:04:07 2013 +0200 |
| tree | 7348799eca051013d1d6b51ae7e5f7c4b231057d | |
| parent | 0b6e8569b7b767f9418f1b043aa5986015a33b21 [diff] |
x86/iommu: correct ICS register offset According to Intel Vt-D specs, the offset of Invalidation complete status register should be 0x9C, not 0x98. See Intel's VT-d spec, Revision 1.3, Chapter 10.4, Page 98; Signed-off-by: Li, Zhen-Hua <zhen-hual@hp.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>