| commit | 82e56393a80b99cf8986616447d71cbcff90e9d1 | [log] [tgz] |
|---|---|---|
| author | Paweł Jarosz <paweljarosz3691@gmail.com> | Fri Nov 04 14:10:56 2016 +0100 |
| committer | Heiko Stuebner <heiko@sntech.de> | Sat Nov 05 23:11:01 2016 +0100 |
| tree | 3ff176f7fa80fb65d008cd8816709b7bedc89368 | |
| parent | 1dfbec3905548a0cbc820a62e1d8adee1c80bd41 [diff] |
clk: rockchip: add 400MHz to rk3066 clock rates table We need this to init PLL_CPLL to 400MHz at boot. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>