| commit | 83fab8ea62ca74eaa51613ba8eeaf925f4f8087c | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Thu Mar 29 11:01:47 2018 +0200 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Mon Apr 16 13:39:45 2018 +0200 |
| tree | 9f813cc07f7fe6f64b401e8ae7bbdab3bd9f5be6 | |
| parent | 2c2557e3901e861c78020a3bb202dffc264119cf [diff] |
clk: renesas: r8a7745: Fix LB clock divider The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On RZ/G1E, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>