tree 5d0f1cfc0b37e7d00fa480ad77461a5af22b9683
parent c80f52847c50109ca248c22efbf71ff10553dca4
author Sonic Zhang <sonic.zhang@analog.com> 1369737669 +0800
committer Wolfram Sang <wsa@the-dreams.de> 1371062347 +0200

i2c: bfin-twi: Read and write the FIFO in loop

TWI transfer interrupts may be lost when system is heavily handling other
interrupts, while current transfer handler depends on each accurate interrupt
and misses some data in this case. Because there are 2 2-byte FIFOs in blackfin
TWI controller, the occurrence of the data loss can be reduced by reading till
the RX FIFO is empty and writing till the TX FIFO is full.

Reported-by: Bob Maris <mail@maris-ee.eu>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>