| commit | 89f1b1c614253d7ea57543f769d93fced99d4d05 | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Thu Sep 29 13:06:15 2016 +0200 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Thu Mar 30 13:25:43 2017 +0200 |
| tree | 50846be8db002a74703ba48cb499a2956e99dd10 | |
| parent | 48d0341e41870bcfc42206d38e00a6b1c2fea929 [diff] |
clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
Add all R-Car H3 ES2.0 Clock Pulse Generator Core Clock Outputs, as
listed in Table 8.2a ("List of Clocks [R-Car H3]") of the R-Car Gen3
Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>