| commit | 8ffe93a5b2cb55d4da9c285d9277699bdb828b47 | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Tue Jun 02 14:33:46 2015 +0200 |
| committer | Simon Horman <horms+renesas@verge.net.au> | Fri Feb 19 14:52:22 2016 +0900 |
| tree | 873ad3e0e94e30f402c550fe694fa41b6f22e407 | |
| parent | fb1cecd40690e61e122d7249e7499c8d799feffb [diff] |
ARM: dts: r8a7791: Add L2 cache-controller node Add a device node for the L2 cache, and link the CPU nodes to it. The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as 64 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>