clk: samsung: exynos7: add gate clock for ADC block
Add clock support for the ADC interface in Exynos7.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index f255bb7..8e4681b 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -55,7 +55,8 @@
#define PCLK_HSI2C11 9
#define PCLK_PWM 10
#define SCLK_PWM 11
-#define PERIC0_NR_CLK 12
+#define PCLK_ADCIF 12
+#define PERIC0_NR_CLK 13
/* PERIC1 */
#define PCLK_UART1 1