commit 93317e8e35b77633d589fe0e132291195757d785
author Viresh Kumar <viresh.kumar@st.com> Thu Mar 03 15:47:22 2011 +0530
committer Vinod Koul <vinod.koul@intel.com> Mon Mar 07 01:12:28 2011 +0530
tree c3419c1a02e3952506ca0af281f9f9c5bc52888d
parent b0c3130d69bda5cd91aa3b3f08e7878df49fde69

dw_dmac: Pass Channel Priority from platform_data

In Synopsys designware, channel priority is programmable. This patch adds
support for passing channel priority through platform data. By default Ascending
channel priority will be followed, i.e. channel 0 will get highest priority and
channel 7 will get lowest.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

drivers/dma/dw_dmac.c

diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index f413e12..318a342 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -901,8 +901,11 @@
 		BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 
 		cfghi = dws->cfg_hi;
-		cfglo = dws->cfg_lo;
+		cfglo = dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
 	}
+
+	cfglo |= DWC_CFGL_CH_PRIOR(dwc->priority);
+
 	channel_writel(dwc, CFG_LO, cfglo);
 	channel_writel(dwc, CFG_HI, cfghi);
 
@@ -1325,6 +1328,12 @@
 		else
 			list_add(&dwc->chan.device_node, &dw->dma.channels);
 
+		/* 7 is highest priority & 0 is lowest. */
+		if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
+			dwc->priority = 7 - i;
+		else
+			dwc->priority = i;
+
 		dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
 		spin_lock_init(&dwc->lock);
 		dwc->mask = 1 << i;