tree bf791a74c0914464a21ede67a075fe71dd93cd74
parent 4d1369cae0165227048c420cf089668335084151
author Chen-Yu Tsai <wens@csie.org> 1512364751 +0800
committer Maxime Ripard <maxime.ripard@free-electrons.com> 1512637784 +0100

clk: sunxi-ng: Support fixed post-dividers on MP style clocks

On the A64, the MMC module clocks are fixed in the new timing mode,
i.e. they do not have a bit to select the mode. These clocks have
a 2x divider somewhere between the clock and the MMC module.

To be consistent with other SoCs supporting the new timing mode,
we model the 2x divider as a fixed post-divider on the MMC module
clocks.

To do this, we first add fixed post-divider to the MP style clocks,
which the MMC module clocks are.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>