| commit | 9473c8f485e1e3740d5aebf1de4838b615f9dedc | [log] [tgz] |
|---|---|---|
| author | Vijay Purushothaman <vijay.a.purushothaman@intel.com> | Thu Sep 27 19:13:01 2012 +0530 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Fri Sep 28 16:42:52 2012 +0200 |
| tree | 545c8f135d6f3ef81fd027811d28ce21b1cd347c | |
| parent | 3bcedbe5f2a3da65326d99803cac71c1e89bc93f [diff] |
drm/i915: Set aux clk to 100MHz for Valleyview Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview. This enables the aux transactions in Valleyview. Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>