tree bcec9d0dd4a6ddca75038cbc44227fb25e05099e
parent b4df480f68ae03b5dd4ab0db56536fbcec741705
author Todd Fujinaka <todd.fujinaka@intel.com> 1404982035 -0700
committer David S. Miller <davem@davemloft.net> 1404982108 -0700

igb: Workaround for i210 Errata 25: Slow System Clock

On some devices, the internal PLL circuit occasionally provides the
wrong clock frequency after power up. The probability of failure is less
than one failure per 1000 power cycles. When the failure occurs, the
internal clock frequency is around 1/20 of the correct frequency.

Cc: stable <stable@vger.kernel.org>
Signed-off-by: Todd Fujinaka <todd.fujinaka@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>