tree 554a4e642438b0ccdeff9f7b4e0b9708083afb78
parent 83f191a7cdf5286a8f3745e847f50c29fa349da9
author Padmavathi Venna <padma.v@samsung.com> 1421148460 +0530
committer Sylwester Nawrocki <s.nawrocki@samsung.com> 1421331100 +0100

clk: samsung: exynos7: add gate clock for DMA block

Add support for PDMA0 and PDMA1 gate clks.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>