Merge branch 'pci/host-xilinx' into next
* pci/host-xilinx:
PCI: xilinx-nwl: Remove mask for messages not supported by AXI
PCI: xilinx: Configure PCIe MPS settings
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index 43eaa4a..4c3e0ab 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -62,21 +62,9 @@
#define CFG_ENABLE_PM_MSG_FWD BIT(1)
#define CFG_ENABLE_INT_MSG_FWD BIT(2)
#define CFG_ENABLE_ERR_MSG_FWD BIT(3)
-#define CFG_ENABLE_SLT_MSG_FWD BIT(5)
-#define CFG_ENABLE_VEN_MSG_FWD BIT(7)
-#define CFG_ENABLE_OTH_MSG_FWD BIT(13)
-#define CFG_ENABLE_VEN_MSG_EN BIT(14)
-#define CFG_ENABLE_VEN_MSG_VEN_INV BIT(15)
-#define CFG_ENABLE_VEN_MSG_VEN_ID GENMASK(31, 16)
#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
CFG_ENABLE_INT_MSG_FWD | \
- CFG_ENABLE_ERR_MSG_FWD | \
- CFG_ENABLE_SLT_MSG_FWD | \
- CFG_ENABLE_VEN_MSG_FWD | \
- CFG_ENABLE_OTH_MSG_FWD | \
- CFG_ENABLE_VEN_MSG_EN | \
- CFG_ENABLE_VEN_MSG_VEN_INV | \
- CFG_ENABLE_VEN_MSG_VEN_ID)
+ CFG_ENABLE_ERR_MSG_FWD)
/* Misc interrupt status mask bits */
#define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index c8616fa..7f030f5 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -632,7 +632,7 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct xilinx_pcie_port *port;
- struct pci_bus *bus;
+ struct pci_bus *bus, *child;
int err;
resource_size_t iobase = 0;
LIST_HEAD(res);
@@ -686,6 +686,8 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
#ifndef CONFIG_MICROBLAZE
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
#endif
+ list_for_each_entry(child, &bus->children, node)
+ pcie_bus_configure_settings(child);
pci_bus_add_devices(bus);
return 0;