tree 81e8e9ea897a7ab9aa32e7bbfc56ca62423b119e
parent e429817b401f095ac483fcb02524b01faf45dad6
author Will Deacon <will.deacon@arm.com> 1425642849 +0000
committer Will Deacon <will.deacon@arm.com> 1427209677 +0000

ARM: pmu: add support for interrupt-affinity property

Historically, the PMU devicetree bindings have expected SPIs to be
listed in order of *logical* CPU number. This is problematic for
bootloaders, especially when the boot CPU (logical ID 0) isn't listed
first in the devicetree.

This patch adds a new optional property, interrupt-affinity, to the
PMU node which allows the interrupt affinity to be described using
a list of phandled to CPU nodes, with each entry in the list
corresponding to the SPI at the same index in the interrupts property.

Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>