tree 612a53e387a6aea6116f8a1637050fa13c6d9f80
parent 074d82cf688fe2dfa7ba4a2317c56f62d13fb522
author David S. Miller <davem@davemloft.net> 1140733168 -0800
committer David S. Miller <davem@sunset.davemloft.net> 1142846040 -0800

[SPARC64]: Fix TLB context allocation with SMT style shared TLBs.

The context allocation scheme we use depends upon there being a 1<-->1
mapping from cpu to physical TLB for correctness.  Chips like Niagara
break this assumption.

So what we do is notify all cpus with a cross call when the context
version number changes, and if necessary this makes them allocate
a valid context for the address space they are running at the time.

Stress tested with make -j1024, make -j2048, and make -j4096 kernel
builds on a 32-strand, 8 core, T2000 with 16GB of ram.

Signed-off-by: David S. Miller <davem@davemloft.net>