| commit | a168b8f1cde6588ff7a67699fa11e01bc77a5ddd | [log] [tgz] |
|---|---|---|
| author | Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> | Wed Nov 19 09:29:42 2014 +0000 |
| committer | Markos Chandras <markos.chandras@imgtec.com> | Mon Feb 16 14:02:50 2015 +0000 |
| tree | c7c8e42b220c8a2af11c7aa99d14ad5e8fd8954b | |
| parent | 51eec48e1252ea39d21b5206e4962f09f823a369 [diff] |
MIPS: mm: Add MIPS R6 instruction encodings MIPS R6 defines new opcodes for ll, sc, cache and pref instructions so we need to take these into consideration in the micro-assembler. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>