tree c7c8e42b220c8a2af11c7aa99d14ad5e8fd8954b
parent 51eec48e1252ea39d21b5206e4962f09f823a369
author Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> 1416389382 +0000
committer Markos Chandras <markos.chandras@imgtec.com> 1424095370 +0000

MIPS: mm: Add MIPS R6 instruction encodings

MIPS R6 defines new opcodes for ll, sc, cache and pref instructions
so we need to take these into consideration in the micro-assembler.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>