ARM: dts: msm: update embedded UFS device related DT properties on Kona
This change removes embedded UFS's PHY ref_clk per Kona UFS PHY design.
It also changes UFS PHY AUX clock and UFS mem AXI/UniPro/ICE clocks to
their HW_CTL clocks and updates the UFS ICE core clock minsvs_freq.
Change-Id: I8e52a3fad384d4e06c41a6bae8a8a933e07fbf79
Signed-off-by: Can Guo <cang@codeaurora.org>
diff --git a/arch/arm64/boot/dts/qcom/kona.dtsi b/arch/arm64/boot/dts/qcom/kona.dtsi
index 8333308..850e1bc 100644
--- a/arch/arm64/boot/dts/qcom/kona.dtsi
+++ b/arch/arm64/boot/dts/qcom/kona.dtsi
@@ -1738,11 +1738,9 @@
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
- "ref_clk",
"ref_aux_clk";
clocks = <&clock_rpmh RPMH_CXO_CLK>,
- <&clock_gcc GCC_UFS_1X_CLKREF_EN>,
- <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ <&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>;
status = "disabled";
};
@@ -1768,11 +1766,11 @@
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
- <&clock_gcc GCC_UFS_PHY_AXI_CLK>,
- <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>,
+ <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK>,
<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
- <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
- <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>,
+ <&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
@@ -1782,7 +1780,7 @@
<0 0>,
<0 0>,
<37500000 300000000>,
- <75000000 300000000>,
+ <37500000 300000000>,
<0 0>,
<0 0>,
<0 0>,