tree 8916cb64f4260283d7bc9cfeefc3a254b7a113ca
parent 7e57fd1444bf8f4ba9179f826ed6817c56b801d4
author Gabriele Paoloni <gabriele.paoloni@huawei.com> 1460804619 +0100
committer Bjorn Helgaas <bhelgaas@google.com> 1462223508 -0500

PCI: designware: Remove incorrect RC memory base/limit configuration

Currently dw_pcie_setup_rc() configures memory base and memory limit in the
type1 configuration header for the root complex.  In doing so it uses the
CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr).
This is wrong and it is useless since the configuration is overwritten
later on when pci_bus_assign_resources() is called.

Remove this configuration from dw_pcie_setup_rc().

Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>