tree d5a078e15b1db6eaf2ae49570ae5acb7cd9b0e80
parent 369602d370fac9d3bda125c8cc36c8f779910bf1
author Gaurav K Singh <gaurav.k.singh@intel.com> 1417769021 +0530
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1417789700 +0100

drm/i915: Pixel Clock changes for DSI dual link

For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.

v2 : Address review comments by Jani
     - Removed the bit mask used for ->dual_link
     - Used DSI instead of MIPI for #define variables

v3: Added the VLV_DISPLAY_BASE to VLV_CHICKEN_3 register

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>